Deeply recessed top metal gate for gate-all-around field effect transistor
A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a vertical metal gate disposed between a first and second source/drain (S/D) epitaxial (EPI) structure and having a set of vertically-stacked, horizontal channels connecting the first and second S/D EPI structures through the vertical metal gate, where a top-most portion of the vertical metal gate is above a top-most channel. A high-K dielectric material is disposed between the vertical metal gate and each of the horizontal channels, and vertical spacer layers separate the vertical metal gate from the S/D EPI structures. A low-K dielectric structure is disposed above the top-most portion of the vertical metal gate and fills a recess above the vertical metal gate and between the first vertical spacer layer and the second vertical spacer layer.
1 . A field effect transistor (FET) structure, comprising:
a vertical metal gate structure extending in a first horizontal direction and having a first portion disposed between a first source/drain (S/D) epitaxial (EPI) structure and a second S/D EPI structure set apart in a second horizontal direction and comprising a first channel structure, the first channel structure comprising a first plurality of vertically-stacked, horizontal channels connecting the first S/D EPI structure to the second S/D EPI structure in the second horizontal direction through the first portion of the vertical metal gate structure, wherein a top-most portion of the vertical metal gate structure is above a first top-most channel of the first plurality of vertically-stacked, horizontal channels;
a high-K dielectric material disposed between the vertical metal gate structure and each of the first plurality of vertically-stacked, horizontal channels;
a first vertical spacer layer extending in the first horizontal direction and disposed between the vertical metal gate structure and the first S/D EPI structure;
a second vertical spacer layer extending in the first horizontal direction and disposed between the vertical metal gate structure and the second S/D EPI structure; and
a low-K dielectric structure disposed above the top-most portion of the vertical metal gate structure and between the first vertical spacer layer and the second vertical spacer layer.
2 . The FET structure of claim 1 , wherein the low-K dielectric structure fills a recess formed by the first vertical spacer layer, the second vertical spacer layer, and the top-most portion of the vertical metal gate structure.
3 . The FET structure of claim 1 , wherein the vertical metal gate structure comprises a gate-all-around (GAA) structure.
4 . The FET structure of claim 1 , further comprising a frontside inter-layer dielectric (ILD) layer disposed above the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure.
5 . The FET structure of claim 1 ,
wherein a second portion of the vertical metal gate structure is disposed between a third S/D EPI structure and a fourth S/D EPI structure set apart in the second horizontal direction and set apart from the first S/D EPI structure and the second S/D EPI structure in the first horizontal direction and comprising a second channel structure, the second channel structure comprising a second plurality of vertically-stacked, horizontal channels connecting the third S/D EPI structure to the fourth S/D EPI structure in the second horizontal direction through the vertical metal gate structure,
wherein the top-most portion of the vertical metal gate structure is above a second top-most channel of the second plurality of vertically-stacked, horizontal channels.
6 . The FET structure of claim 5 , wherein the vertical metal gate structure comprises a third portion between the first portion of the vertical metal gate structure and the second portion of the vertical metal gate structure, wherein a top surface of the third portion of the vertical metal gate structure is below a top surface of the first portion of the vertical metal gate structure.
7 . The FET structure of claim 6 , wherein the top surface of the third portion is below the first top-most channel of the first plurality of vertically-stacked, horizontal channels.
8 . A method of fabricating a field effect transistor (FET) structure, the method comprising:
providing a vertical metal gate structure extending in a first horizontal direction and having a first portion disposed between a first source/drain (S/D) epitaxial (EPI) structure and a second S/D EPI structure set apart in a second horizontal direction and comprising a first channel structure, the first channel structure comprising a first plurality of vertically-stacked, horizontal channels connecting the first S/D EPI structure to the second S/D EPI structure in the second horizontal direction through the first portion of the vertical metal gate structure, wherein a top-most portion of the vertical metal gate structure is above a first top-most channel of the first plurality of vertically-stacked, horizontal channels;
providing a high-K dielectric material disposed between the vertical metal gate structure and each of the first plurality of vertically-stacked, horizontal channels;
providing a first vertical spacer layer extending in the first horizontal direction and disposed between the vertical metal gate structure and the first S/D EPI structure;
providing a second vertical spacer layer extending in the first horizontal direction and disposed between the vertical metal gate structure and the second S/D EPI structure; and
providing a low-K dielectric structure disposed above the top-most portion of the vertical metal gate structure and between the first vertical spacer layer and the second vertical spacer layer.
9 . The method of claim 8 , wherein providing the low-K dielectric structure comprises filling a recess formed by the first vertical spacer layer, the second vertical spacer layer, and the top-most portion of the vertical metal gate structure.
10 . The method of claim 8 , wherein providing the vertical metal gate structure comprises providing a gate-all-around (GAA) structure.
11 . The method of claim 8 , further comprising providing a frontside inter-layer dielectric (ILD) layer disposed above the vertical metal gate structure, the first S/D EPI structure, and the second S/D EPI structure.
12 . The method of claim 8 , further comprising:
providing a second portion of the vertical metal gate structure is disposed between a third S/D EPI structure and a fourth S/D EPI structure set apart in the second horizontal direction and set apart from the first S/D EPI structure and the second S/D EPI structure in the first horizontal direction and comprising a second channel structure, the second channel structure comprising a second plurality of vertically-stacked, horizontal channels connecting the third S/D EPI structure to the fourth S/D EPI structure in the second horizontal direction through the vertical metal gate structure,
wherein the top-most portion of the vertical metal gate structure is above a second top-most channel of the second plurality of vertically-stacked, horizontal channels.
13 . The method of claim 12 , wherein the vertical metal gate structure comprises a third portion between the first portion of the vertical metal gate structure and the second portion of the vertical metal gate structure, wherein a top surface of the third portion of the vertical metal gate structure is below a top surface of the first portion of the vertical metal gate structure.
14 . The method of claim 13 , wherein the top surface of the third portion is below the first top-most channel of the first plurality of vertically-stacked, horizontal channels.