Semiconductor device including fin field-effect transistors on active fins with different gate width in boundary region

1 . A semiconductor device, comprising:

a substrate including a first region and a second region;

a first active fin extending in a first direction on the first region of the substrate;

a second active fin extending in the first direction on the second region of the substrate;

an isolation pattern on the substrate between the first region and the second region;

a first gate structure on the first active fin, the first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure extending onto an upper surface of the isolation pattern;

a second gate structure on the second active fin, the second gate structure extending in the second direction, and the second gate structure extending onto the upper surface of the isolation pattern,

wherein a first end in the second direction of the first gate structure and a second end in the second direction of the second gate structure facing the first end are spaced apart from each other in the second direction,

wherein the first gate structure and the second gate structure are physically separated from each other,

wherein the first gate structure includes a first portion having a first width and a second portion having a second width that is less than the first width,

wherein the second gate structure includes a third portion having the first width and a fourth portion having the second width, and

wherein the second portion includes the first end, and the fourth portion includes the second end.

2 . The semiconductor device as claimed in claim 1 , wherein:

the second portion of the first gate structure is on the isolation pattern, and

the fourth portion of the second gate structure is on the isolation pattern.

3 . The semiconductor device as claimed in claim 1 , wherein:

the first portion of the first gate structure is on the first active fin and on the isolation pattern adjacent to the first region, and

the third portion of the second gate structure is on the second active fin and on the isolation pattern adjacent to the second region.

4 . The semiconductor device as claimed in claim 1 , wherein the first gate structure and the second gate structure are aligned with each other in the second direction.

5 . The semiconductor device as claimed in claim 1 , further comprising:

a first semiconductor structure on the first active fin adjacent to both sides of the first gate structure;

a first metal pattern extending in the second direction, the first metal pattern contacting the first semiconductor structure;

a second semiconductor structure on the second active fin adjacent to both sides of the second gate structure; and

a second metal pattern extending in the second direction, the second metal pattern contacting the second semiconductor structure.

6 . The semiconductor device as claimed in claim 5 , wherein:

the first metal pattern is on the first region, and

the second metal pattern is on the second region.

7 . The semiconductor device as claimed in claim 1 , further comprising:

an opening extending in the first direction and being between the first gate structure and the second gate structure in the second direction, and

an insulation pattern extending in the first direction and filling the opening.

8 . The semiconductor device as claimed in claim 7 , wherein a bottom surface of the insulation pattern contacts the isolation pattern.

9 . The semiconductor device as claimed in claim 7 , wherein the first end of the first gate structure and the second end of the second gate structure contact sidewalls of the insulation pattern, respectively.

10 . A semiconductor device, comprising:

a substrate including a first region, a second region, and a boundary region between the first region and the second region;

first active fins on the first region of the substrate, the first active fins extending in a first direction;

second active fins on the second region of the substrate, the second active fins extending in the first direction;

an isolation pattern on the boundary region of the substrate;

first gate structures on the first active fins, the first gate structures extending in a second direction perpendicular to the first direction, and the first gate structures extending onto an upper surface of the isolation pattern;

second gate structures on the second active fins, the second gate structures extending in the second direction, and the second gate structures extending onto the upper surface of the isolation pattern;

a first semiconductor structure on the first active fins adjacent to both sides of each of the first gate structures;

a first metal pattern extending in the second direction, the first metal pattern contacting the first semiconductor structure;

a second semiconductor structure on the second active fins adjacent to both sides of each of the second gate structures; and

a second metal pattern extending in the second direction, the second metal pattern contacting the second semiconductor structure,

wherein a portion of each of the first gate structures on the isolation pattern has a width that is less than a width of other portion of each of the first gate structures, and

wherein a portion of each of the second gate structures on the isolation pattern has a width that is less than a width of other portion of each of the second gate structures.

11 . The semiconductor device as claimed in claim 10 , wherein:

each of the first gate structures includes a first portion having a first width and a second portion having a second width that is less than the first width, the second portion being on the isolation pattern, and

each of the second gate structures includes a third portion having the first width and a fourth portion having the second width, the fourth portion being on the isolation pattern.

12 . The semiconductor device as claimed in claim 11 , wherein:

the first portion of each of the first gate structures is on the first active fins and on the isolation pattern adjacent to the first region, and

the third portion of each of the second gate structures is on the second active fins and on the isolation pattern adjacent to the second region.

13 . The semiconductor device as claimed in claim 10 , further comprising:

an opening extending in the first direction and being between each of the first gate structures and each of the second gate structures in the second direction; and

an insulation pattern extending in the first direction and filling the opening.

14 . The semiconductor device as claimed in claim 10 , further comprising:

a first isolation pattern between the first active fins; and

a second isolation pattern between the second active fins,

wherein upper portions of the first active fins protrude from the first isolation pattern, and

wherein upper portions of the second active fins protrude from the second isolation pattern.

15 . A semiconductor device, comprising:

a substrate including a first region, a second region, and a boundary region between the first region and the second region;

an isolation pattern on the boundary region of the substrate;

a first gate structure on the first region of the substrate, the first gate structure extending in a second direction, and a first end in the second direction of the first gate structure being on the isolation pattern of the boundary region adjacent to the first region; and

a second gate structure on the second region of the substrate, the second gate structure extending in the second direction, and a second end in the second direction of the second gate structure being on the isolation pattern of a boundary region adjacent to the second region,

wherein the first end and the second end facing the first end are spaced apart from each other in the second direction,

wherein the first gate structure and the second gate structure are physically separated from each other,

wherein the first gate structure includes a first portion having a first width and a second portion having a second width that is less than the first width, the second portion being on the isolation pattern,

wherein the second gate structure includes a third portion having the first width and a fourth portion having the second width, the fourth portion being on the isolation pattern, and

wherein the second portion includes the first end, and the fourth portion includes the second end.

16 . The semiconductor device as claimed in claim 15 , further comprising first active fins on the first region and second active fins on the second region, wherein:

the first portion of the first gate structure is on the first active fins and on the isolation pattern adjacent to the first region, and

the third portion of the second gate structure is on the second active fins and on the isolation pattern adjacent to the second region.

17 . The semiconductor device as claimed in claim 15 , further comprising:

an opening extending in a first direction perpendicular to the second direction and being between the first gate structure and the second gate structure in the second direction, and

an insulation pattern extending in the first direction and filling the opening.

18 . The semiconductor device as claimed in claim 15 , further comprising:

first active fins on the first region of the substrate, the first active fins extending in a first direction perpendicular to the second direction;

second active fins on the second region of the substrate, the second active fins extending in the first direction;

a first semiconductor structure on the first active fins adjacent to both sides of the first gate structure; and

a second semiconductor structure on the second active fins adjacent to both sides of the second gate structure,

wherein the first active fins are disposed under the first semiconductor structure and the second active fins are disposed under the second semiconductor structure, and

wherein the first semiconductor structure includes a source/drain region of a p-type transistor and the second semiconductor structure includes a source/drain region of an n-type transistor.

19 . The semiconductor device as claimed in claim 18 , further comprising:

a first isolation pattern between the first active fins on the first region of the substrate; and

a second isolation pattern between the second active fins on the second region of the substrate.

20 . The semiconductor device as claimed in claim 15 , further comprising:

a first nanosheet structure on the first region of the substrate, the first nanosheet structure including first nanosheets spaced apart from each other in a vertical direction; and

a second nanosheet structure on the second region of the substrate, the second nanosheet structure including second nanosheets spaced apart from each other in the vertical direction.