Semiconductor device and manufacturing method thereof

1 . A method of forming a semiconductor device, comprising:

forming semiconductor channel layers over a semiconductor substrate, wherein the semiconductor channel layers are vertically stacked and separate apart from one another;

forming an epitaxial source/drain (S/D) structure on the semiconductor substrate, wherein the epitaxial S/D structure is laterally coupled to the semiconductor channel layers;

forming a gate structure around the semiconductor channel layers;

forming a dielectric structure over the gate structure and the epitaxial S/D structure;

forming a trench in the dielectric structure to accessibly expose at least a portion of the epitaxial S/D structure;

forming a contact feature from the portion of the epitaxial S/D structure within the trench comprising:

forming a metal layer in the trench;

performing a thermal process on the metal layer to form the contact feature, wherein after the thermal process and before a wet etching process, metal residues remain on a sidewall of a spacer of the dielectric structure in the trench to expose portions of the spacer of the dielectric structure in the trench; and

removing the metal residues by using the wet etching process, wherein the spacer of the dielectric structure remains substantially intact; and

forming a S/D contact in the trench to be in contact with the contact feature overlying the epitaxial S/D structure.

2 . The method of claim 1 , wherein an etching solution used in the wet etching process has an oxidation potential at least 1.4V.

3 . The method of claim 1 , wherein an etching solution used in the wet etching process is a mixture of hydrochloric acid (HCl) and ozone (O 3 ).

4 . The method of claim 3 , wherein a volume ratio of HCl:O 3 is 1:2 or 2:1.

5 . The method of claim 1 , wherein the wet etching process is performed using an etching solution at a room temperature for about 60 seconds to about 180 seconds.

6 . The method of claim 1 , wherein the metal layer comprises nickel and platinum.

7 . The method of claim 1 , wherein after forming the metal layer, a portion of the metal layer formed on a top surface of the dielectric structure is thicker than a portion of the metal layer formed on the sidewall of the spacer of the dielectric structure.

8 . The method of claim 1 , wherein the contact feature from the portion of the epitaxial S/D structure is a silicide feature or a germanide feature.

9 . The method of claim 1 , wherein the gate structure comprises a plurality of segments, the segments and the semiconductor channel layers are arranged in an alternating manner in a cross-sectional view.

10 . A method of forming a semiconductor device, comprising:

forming an epitaxial source/drain (S/D) structure to be in lateral contact with semiconductor channel layers, wherein the semiconductor channel layers are vertically separated from one another;

forming a gate structure around the semiconductor channel layers;

covering the epitaxial S/D structure and the gate structure with a dielectric structure;

forming a trench in the dielectric structure to accessibly expose at least a portion of the epitaxial S/D structure;

forming a metal layer in the trench;

annealing the metal layer to form a contact feature from the portion of the epitaxial S/D structure within the trench and metal residues remaining on a sidewall of a spacer of the dielectric structure in the trench, wherein after the annealing and before etching the metal residues, the metal residues expose portions of the spacer of the dielectric structure in the trench;

etching the metal residues by an etchant solution having an oxidation potential at least 1.4V; and

forming a S/D contact in the trench to be in contact with the contact feature overlying the epitaxial S/D structure.

11 . The method of claim 10 , wherein the etching solution is a mixture of hydrochloric acid and ozone.

12 . The method of claim 10 , wherein etching the metal residues is performed at a room temperature for about 60 seconds to about 180 seconds.

13 . The method of claim 10 , wherein the metal layer comprises nickel and platinum.

14 . The method of claim 10 , wherein the contact feature from the portion of the epitaxial S/D structure is a silicide feature or a germanide feature.

15 . The method of claim 10 , wherein after etching the metal residues, the spacer of the dielectric structure where the metal residues were formed on remains substantially intact.

16 . A method of forming a semiconductor device, comprising:

forming an epitaxial source/drain (S/D) structure to be in lateral contact with semiconductor channel layers along a first direction, wherein the semiconductor channel layers are separated from one another in a second direction that is substantially perpendicular to the first direction;

forming a gate structure around the semiconductor channel layers;

forming a trench in a dielectric structure that covers the epitaxial S/D structure and the gate structure to accessibly expose at least a portion of the epitaxial S/D structure;

forming a contact spacer on the dielectric structure and in the trench, wherein the contact spacer lands on a periphery of a top surface of the portion of the epitaxial S/D structure;

forming a metal layer in the trench;

reacting the metal layer with the epitaxial S/D structure to form a silicide feature, wherein after the reacting and before a wet etching process, metal residues remain on a sidewall of the contact spacer in the trench to expose portions of the contact spacer in the trench;

selectively removing the metal residues without damaging the contact spacer through the wet etching process; and

forming a metal contact in the trench to be in contact with the contact spacer and the silicide feature overlying the epitaxial S/D structure.

17 . The method of claim 16 , wherein an etching solution used in the wet etching process has an oxidation potential at least 1.4V.

18 . The method of claim 16 , wherein an etching solution used in the wet etching process is a mixture of hydrochloric acid and ozone.

19 . The method of claim 16 , wherein the wet etching process is performed using an etching solution at a room temperature for about 60 seconds to about 180 seconds.

20 . The method of claim 16 , wherein the silicide feature is located below the contact spacer.