IP Library › Granted Patent US 12677471
Granted Patent B2
US 12677471 · App. 17/846,423 · Granted Jul 7, 2026

Enhanced power and signal for stacked-FETs

Inventors: Albert M. Young (Fishkill, NY); Albert M. Chu (Nashua, NH); Junli Wang (Slingerlands, NY)
Assignee: International Business Machines Corporation
H10D84/038H10D84/0167H10D84/0186H10D88/00H10W20/20H10W20/42H10W20/427H10W90/00
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Quick Facts
Patent No.
US 12677471
App. No.
17/846,423
Granted
Jul 7, 2026
Kind
B2
Abstract

A semiconductor structure including a reliable power rail in stacked field effect transistor technology with unequal device footprints is provided that mitigates, and in some cases even eliminates, shorting risks that are typically associated using long bars in advanced logic applications.

Claims (22)

1 . A semiconductor structure comprising:

a stacked field effect transistor having a top field effect transistor located above a bottom field effect transistor, wherein the bottom field effect transistor has a first channel region having a first channel width and the top field effect transistor has a second channel region having a second channel width that is different from the first channel width, and wherein the first channel region of the bottom field effect transistor and the second channel region of the top field effect transistor share a common sidewall;

a first contact structure directly contacting a top surface of a source/drain region of the bottom field effect transistor and extending laterally away from the common sidewall and beyond a sidewall of the source/drain region of bottom field effect transistor; and

a power rail in electrical contact with the first contact structure.

2 . The semiconductor structure of claim 1 , wherein the first channel width is wider than the second channel width.

3 . The semiconductor structure of claim 2 , wherein the top field effect transistor is a p-type field effect transistor and the bottom field effect transistor is an n-type field effect transistor.

4 . The semiconductor structure of claim 2 , wherein the top field effect transistor is an n-type field effect transistor and the bottom field effect transistor is p-type field effect transistor.

5 . The semiconductor structure of claim 2 , wherein the top field effect transistor and the bottom field effect transistor are both n-type field effect transistors.

6 . The semiconductor structure of claim 2 , wherein the top field effect transistor and the bottom field effect transistor are both p-type field effect transistors.

7 . The semiconductor structure of claim 2 , wherein the power rail extends downward from a power source that is located above the top field effect transistor.

8 . The semiconductor structure of claim 2 , further comprising a single line in electrical contact with another first contact structure of a source/drain region of a bottom field effect transistor of an adjacent stacked field effect transistor.

9 . The semiconductor structure of claim 2 , further comprising a second contact structure contacting a source/drain region of the top field effect transistor.

10 . The semiconductor structure of claim 9 , wherein the second contact structure is connected to a power source that is located above the top field effect transistor by a via structure.

11 . The semiconductor structure of claim 1 , wherein the first channel width is narrower than the second channel width.

12 . The semiconductor structure of claim 11 , wherein the top field effect transistor is a p-type field effect transistor and the bottom field effect transistor is an n-type field effect transistor.

13 . The semiconductor structure of claim 11 , wherein the top field effect transistor is an n-type field effect transistor and the bottom field effect transistor is p-type field effect transistor.

14 . The semiconductor structure of claim 11 , wherein the top field effect transistor and the bottom field effect transistor are both n-type field effect transistors.

15 . The semiconductor structure of claim 11 , wherein the top field effect transistor and the bottom field effect transistor are both p-type field effect transistors.

16 . The semiconductor structure of claim 11 , wherein the power rail extends upward from a power source that is located beneath the bottom field effect transistor.

17 . The semiconductor structure of claim 11 , further comprising a single line in electrical contact with another first contact structure of a source/drain region of a bottom field effect transistor of an adjacent stacked field effect transistor.

18 . The semiconductor structure of claim 11 , further comprising a second contact structure contacting a source/drain region of the top field effect transistor.

19 . The semiconductor structure of claim 18 , wherein the second contact structure is connected to a power source that is located above the top field effect transistor by a via structure.