IP Library Granted Patent US 12677473
Granted Patent B2
US 12677473 · App. 18/220,803 · Granted Jul 7, 2026

Semiconductor device and method for fabricating the same

Inventors: Po-Kuang Hsieh (Kaohsiung City, TW); Chien-Ting Lin (Tainan City, TW); Ssu-I Fu (Kaohsiung City, TW); Chin-Hung Chen (Tainan City, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10D84/038H10D84/0135H10D84/84
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Quick Facts
Patent No.
US 12677473
App. No.
18/220,803
Filed
Jul 11, 2023
Granted
Jul 7, 2026
Kind
B2
Art Unit
2898
USPC
257/392
Abstract

A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

Claims (11)

1 . A semiconductor device, comprising:

a substrate having a medium-voltage (MV) region and a low-voltage (LV) region;

a first gate structure on the LV region and a second gate structure on the MV region, wherein a bottom surface of the first gate structure is even with a bottom surface of the second gate structure; and

a first hard mask on the first gate structure and a second hard mask on the second gate structure, wherein the first hard mask and the second hard mask comprise different thicknesses.

2 . The semiconductor device of claim 1 , wherein a surface of the substrate on the LV region is even with a surface of the substrate on the MV region.

3 . The semiconductor device of claim 2 , wherein a bottom surface of the first gate structure is even with a bottom surface of the second gate structure.

4 . The semiconductor device of claim 2 , wherein a thickness of the second hard mask is less than a thickness of the first hard mask.

5 . The semiconductor device of claim 1 , wherein a surface of the substrate on the LV region is higher than a surface of the substrate on the MV region.

6 . The semiconductor device of claim 5 , wherein a bottom surface of the first gate structure is higher than a bottom surface of the second gate structure.

7 . The semiconductor device of claim 5 , wherein a thickness of the first hard mask is less than a thickness of the second hard mask.

8 . The semiconductor device of claim 1 , wherein top surfaces of the first hard mask and the second hard mask are coplanar.