IP Library › Granted Patent US 12677475
Granted Patent B2
US 12677475 · App. 18/614,055 · Granted Jul 7, 2026

Reference voltage circuit

Inventor: Yasuo Matsumura (Osaka, JP)
Assignees: Nexperia B.V.; Nexperia Technology (Shanghai) Ltd.
H10D84/84G05F1/468G05F3/242H10D84/0163H10D84/038H10D84/811
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Quick Facts
Patent No.
US 12677475
App. No.
18/614,055
Granted
Jul 7, 2026
Kind
B2
Abstract

A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.

Claims (37)

1 . A reference voltage generating circuit comprising:

a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET) having a source electrode, a drain electrode, and a gate electrode;

wherein the drain electrode of the first depletion type MOSFET is configured to be connected to a supply potential, and the gate electrode of the first depletion type MOSFET is connected to the source of the first depletion type MOSFET;

a first enhancement type MOSFET having a source electrode, a drain electrode, and a gate electrode, wherein each of the first depletion type MOSFET and the first enhancement type MOSFET comprises a substrate electrode;

wherein the drain electrode of the first enhancement type MOSFET is connected to the source electrode of the first depletion type MOSFET, the gate electrode of the first enhancement type MOSFET is connected to the drain of the first enhancement type MOSFET, and the source electrode of the first enhancement type MOSFET is connected to a first reference potential;

a reference voltage output connected between the source electrode of the first depletion type MOSFET and the drain electrode of the first enhancement type MOSFET;

a second depletion type MOSFET having a source electrode, a drain electrode, and a gate electrode;

a first resistor connected between the source of the first depletion type MOSFET and the substrate electrode of the first depletion type MOSFET; and

a second resistor connected between the source of the first enhancement type MOSFET and the substrate electrode of the first enhancement type MOSFET;

wherein the drain electrode of the second depletion type MOSFET is connected between the supply potential and the drain electrode of the first depletion type MOSFET, and the source electrode of the second depletion type MOSFET is connected between the source electrode of the first depletion type MOSFET and the drain electrode of the first enhancement type MOSFET;

wherein the first resistor has a resistance, and the second resistor has a resistance that have a ratio that is configured so that a voltage of the reference voltage output decreases with increasing temperature; and

wherein the gate of the second depletion type MOSFET is connected to the source of the first enhancement type MOSFET.

2 . The reference voltage generating circuit according to claim 1 , wherein each of the first depletion type MOSFET and the first enhancement type MOSFET comprise N-channel MOSFETs.

3 . The reference voltage generating circuit according to claim 1 , wherein the resistance of the first resistor is less than the resistance of the second resistor.

4 . The reference voltage generating circuit according to claim 1 , wherein the second depletion type MOSFET comprises a substrate electrode.

5 . The reference voltage generating circuit according to claim 2 , wherein the second depletion type MOSFET comprises a substrate electrode.

6 . The reference voltage generating circuit according to claim 3 , wherein the second depletion type MOSFET comprises a substrate electrode.

7 . The reference voltage generating circuit according to claim 4 , wherein the second depletion type MOSFET comprises an N-channel MOSFET.

8 . The reference voltage generating circuit according to claim 4 , further comprising a third resistor connected between the source of the second depletion type MOSFET and the substrate electrode of the second depletion type MOSFET.

9 . The reference voltage generating circuit according to claim 7 , further comprising a third resistor connected between the source of the second depletion type MOSFET and the substrate electrode of the second depletion type MOSFET.

10 . The reference voltage generating circuit according to claim 1 , wherein the source of the second depletion type MOSFET is connected between the drain of the first enhancement type MOSFET and the reference voltage output.

11 . The reference voltage generating circuit according to claim 1 , further comprising:

one or more additional first depletion type MOSFETs connected in series with the first depletion type MOSFET;

one or more additional first enhancement type MOSFETs connected in series with the first enhancement type MOSFET; and

one or more additional second depletion type MOSFETs connected in parallel with the second depletion type MOSFET.

12 . A method of manufacturing a reference voltage generating circuit, the method comprising the steps of:

forming a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET) having a source electrode, a drain electrode, and a gate electrode;

wherein the drain electrode of the first depletion type MOSFET is configured to be connected to a supply potential, and the gate electrode of the first depletion type MOSFET is connected to the source of the first depletion type MOSFET;

forming a first enhancement type MOSFET having a source electrode, a drain electrode, and a gate electrode, wherein each of the first depletion type MOSFET and the first enhancement type MOSFET comprises a substrate electrode;

wherein the drain electrode of the first enhancement type MOSFET is connected to the source electrode of the first depletion type MOSFET, the gate electrode of the first enhancement type MOSFET is connected to the drain of the first enhancement type MOSFET, and the source electrode of the first enhancement type MOSFET is connected to a first reference potential;

forming a reference voltage output connected between the source electrode of the first depletion type MOSFET and the drain electrode of the first enhancement type MOSFET;

forming a second depletion type MOSFET having a source electrode, a drain electrode, and a gate electrode;

forming a first resistor connected between the source of the first depletion type MOSFET and the substrate electrode of the first depletion type MOSFET; and

forming a second resistor connected between the source of the first enhancement type MOSFET and the substrate electrode of the first enhancement type MOSFET;

wherein the drain electrode of the second depletion type MOSFET is connected between the supply potential and the drain electrode of the first depletion type MOSFET, and the source electrode of the second depletion type MOSFET is connected between the source electrode of the first depletion type MOSFET and the drain electrode of the first enhancement type MOSFET;

wherein the first resistor has a resistance and the second resistor has a resistance, that has a ratio that is configured so that a voltage of the reference voltage output decreases with increasing temperature; and

wherein the gate of the second depletion type MOSFET is connected to the source of the first enhancement type MOSFET.