Semiconductor structure and method for forming the same
Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first channel layers formed over a substrate along a first direction, and second channel layers adjacent to the first channel layers and over the substrate. The semiconductor structure includes a first gate structure formed over the first channel layers along a second direction. The semiconductor structure also includes a first gate spacer layer formed adjacent to the first gate structure, and a first thickness of the first channel layers directly below the first gate structure is smaller than a second thickness of the second channel layers directly below the first gate spacer layer
1 . A semiconductor structure, comprising:
first nanostructures formed over a substrate along a first direction;
second nanostructures adjacent to the first nanostructures along the first direction;
a first gate structure formed over the first nanostructures along a second direction, at least one of the first nanostructures comprising:
a first portion underlying the first gate structure; and
a second portion extending outward from the first gate structure along the first direction; and
a second gate structure formed over the second nanostructures along the second direction, at least one of the second nanostructures comprising:
a third portion underlying the second gate structure; and
a fourth portion extending outward from the second gate structure along the first direction;
wherein the first portion has a first thickness along a vertical direction, the second portion has a second thickness along the vertical direction, the third portion has a third thickness along the vertical direction, the fourth portion has a fourth thickness along the vertical direction, and the first thickness is smaller than the second thickness, the third thickness, and the fourth thickness.
2 . The semiconductor structure as claimed in claim 1 , further comprising:
a first gate spacer layer adjacent to the first gate structure, wherein each of the first nanostructures has the second thickness directly below the first gate spacer layer.
3 . The semiconductor structure as claimed in claim 2 , wherein the first gate structure has a continuous sidewall surface in direct contact with the gate spacer layer, and a bottom surface of the continuous sidewall surface of the first gate structure is lower than a bottom surface of the first gate spacer layer.
4 . The semiconductor structure as claimed in claim 1 , wherein a first number of the first nanostructures directly below the first gate structure is smaller than a second number of the second nanostructures directly below the second gate structure.
5 . The semiconductor structure as claimed in claim 1 , further comprising:
third nanostructures formed adjacent to the second nanostructures, wherein each of the third nanostructures has a third width along the second direction, and the second width is smaller than the third width.
6 . The semiconductor structure as claimed in claim 5 , wherein:
at least one of the third nanostructures comprises:
a fifth portion underlying a third gate structure and having a fifth thickness; and
a sixth portion extending outward from the third gate structure along the first direction and having a sixth thickness;
wherein the third thickness is smaller than the fifth thickness.
7 . The semiconductor structure as claimed in claim 1 , further comprising:
a dielectric structure formed between the first gate structure and the second gate structure, wherein a bottom surface of the dielectric structure is lower than a bottommost surface of the first gate structure.
8 . The semiconductor structure as claimed in claim 1 , further comprising:
a first S/D structure formed adjacent to the first gate structure; and
a second S/D structure formed adjacent to the second gate structure, wherein the first S/D structure has a first depth, the second S/D structure has a second depth, and the first depth is smaller than the second depth.
9 . The semiconductor structure as claimed in claim 1 , further comprising:
a semiconductor material layer formed below a bottommost first nanostructure, wherein the semiconductor material layer and the first bottommost first nanostructure are made of different materials.
10 . A semiconductor structure, comprising:
first channel layers positioned over a substrate along a first direction;
second channel layers positioned over the substrate and adjacent to the first channel layers;
a first gate structure formed over the first channel layers along a second direction;
a second gate structure over the second channel layers along the second direction;
a first gate spacer layer formed adjacent to the first gate structure, wherein a first thickness of a first channel layer of the first channel layers underlying the first gate structure is smaller than a second thickness of the first channel layer underlying the first gate spacer layer; and
a second gate spacer layer adjacent to the second gate structure, wherein the first thickness of the first channel layer is smaller than a third thickness of a second channel layer of the second channel layers underlying the second gate structure and is smaller than a fourth thickness of the second channel layer underlying the second gate spacer layer.
11 . The semiconductor structure as claimed in claim 10 , wherein each of the first channel layers has a first width along the second direction, each of the second channel layers has a second width along the second direction, and the first width is smaller than the second width.
12 . The semiconductor structure as claimed in claim 11 , further comprising:
third channel layers adjacent to the second channel layers, wherein each of the third channel layers has a third width along the second direction, and the second width is smaller than the third width.
13 . The semiconductor structure as claimed in claim 10 , wherein the first gate structure has a continuous sidewall surface in direct contact with the first gate spacer layer, and a bottom surface of the continuous sidewall surface of the first gate structure is lower than a bottom surface of the gate spacer layer.
14 . The semiconductor structure as claimed in claim 10 , further comprising:
a first S/D structure formed adjacent to the first channel layers; and
a second S/D structure formed adjacent to the second channel layers, wherein the first S/D structure has a first depth, the second S/D structure has a second depth, and the first depth is smaller than the second depth.
15 . The semiconductor structure as claimed in claim 10 , further comprising:
a first dielectric structure and a second dielectric structure formed between the first gate structure and the second gate structure, wherein a bottom surface of the first dielectric structure is lower than a bottommost surface of the first gate structure.
16 . The semiconductor structure as claimed in claim 10 , further comprising:
a semiconductor material layer formed below a bottommost first channel layer, wherein the semiconductor material layer and the bottommost first channel layer are made of different materials.
17 . The semiconductor structure as claimed in claim 10 , wherein a first number of the first channel layers is smaller than a second number of the second channel layers.
18 . A method for forming a semiconductor structure, comprising:
forming a first fin structure over a first region of a substrate, the first fin structure comprising first semiconductor material layers and second semiconductor material layers alternately stacked;
forming a second fin structure over a second region of the substrate, the second fin structure comprising third semiconductor material layers and fourth semiconductor material layers alternately stacked;
forming a first dummy gate structure over the first fin structure;
forming a second dummy gate structure over the second fin structure;
forming a first gate spacer layer adjacent to the first dummy gate structure;
removing the first dummy gate structure and the second dummy gate structure to expose the first fin structure and the second fin structure;
removing the second semiconductor material layers to form a first opening exposing the first semiconductor material layers;
removing the fourth semiconductor material layers to form a second opening exposing the third semiconductor material layers;
forming a mask covering the third semiconductor material layers and exposing the first semiconductor material layers;
removing portions of the first semiconductor material layers in the first region through the mask to form an expanded first opening;
forming a first gate structure in the expanded first opening to surround the first semiconductor material layers; and
forming a second gate structure in the second opening to surround the third semiconductor material layers, wherein each of the first semiconductor material layers has a first thickness underlying the first gate structure in the first region, each of the third semiconductor material layers has a second thickness underlying the second gate structure in the second region, and the first thickness is smaller than the second thickness.
19 . The method for forming the semiconductor structure as claimed in claim 18 , wherein each of the first semiconductor material layers has a third thickness underlying the first gate spacer layer, and the third thickness is greater than the first thickness.
20 . The method for forming the semiconductor structure as claimed in claim 18 , further comprising:
forming a first S/D structure adjacent to the first dummy gate structure in the first region; and
forming a second S/D structure adjacent to the second dummy gate structure in the second region, wherein the first S/D structure has a first depth, the second S/D structure has a second depth, and the first depth is smaller than the second depth.