Image sensing device and methods of manufacturing the same
Image sensing devices according to present disclosure include metal gate structures in a pixel device. Particularly, the metal gate structures include a ferroelectric layer and a conductive layer to form a negative capacitance device in the gate stack. As a result, the transistors in the pixel device have reduced threshold swing, improved gain and reduced threshold voltage shift. The pixel device according to the present disclosure includes a combination of metal gate and polycrystalline gate, which provides flexibility in pixel device design and improves performance.
1 . A method for forming an image sensing device, comprising:
providing a substrate;
forming an isolation structure in the substrate to define a pixel device region therein;
forming two or more first gate structures over the pixel device region;
doping the substrate to form source/drain regions on opposite sides of the two or more first gate structures;
removing at least one of the two or more first gate structures; and
forming a second gate structure in place of removed first gate structure, wherein the second gate structure and the first gate structures have different arrangement of material layers, and the second gate structure comprises a ferroelectric layer.
2 . The method of claim 1 , wherein forming the second gate structure comprises:
depositing a high-k gate dielectric layer;
depositing an inner gate electrode layer over the high-k gate dielectric layer;
depositing the ferroelectric layer on the inner gate electrode layer; and
depositing a top electrode layer on the ferroelectric layer.
3 . The method of claim 2 , wherein forming the first gate structures comprises:
depositing a gate dielectric layer on the substrate;
depositing a gate electrode layer on the gate dielectric layer, wherein the gate electrode layer comprises a polycrystalline silicon; and
patterning the gate electrode layer and the gate dielectric layer to form the two or more first gate structures from the gate electrode layer and the gate dielectric layer.
4 . The method of claim 3 , wherein forming the two or more first gate structures comprises: forming a transfer gate, a reset gate, a source-follower gate, and a select gate on the substrate over the pixel device region.
5 . The method of claim 4 , wherein doping the substrate comprises:
doping the substrate to form a radiation region, a floating diffusion region, wherein the radiation region and the floating diffusion region are on opposite sides of the transfer gate; and
doping the substrate to form doped regions on opposite sides of the reset gate, the source-follower gate, and the select gate.
6 . The method of claim 4 , wherein removing at least one of the two or more first gate structures comprises:
forming a photoresist layer to cover the transfer gate; and
removing at least one of the reset gate, the source-follower gate and the select gate.
7 . A method of forming a pixel device, comprising:
forming a radiation region, a floating diffusion region, and two or more doped regions in a semiconductor substrate;
forming a first gate structure on the semiconductor substrate, wherein the first gate structure overlaps with the radiation region and the floating diffusion region, wherein forming the first gate structure comprises:
depositing a first gate dielectric layer on the semiconductor substrate; and
depositing a first gate electrode layer on the first gate dielectric layer, wherein the first gate electrode layer comprises a polycrystalline silicon; and
forming a second gate structure on the semiconductor substrate, wherein the second gate structure overlaps with the two or more doped regions, the first gate structure and the second gate structure include different arrangements of material layers, and at least one of the first gate structure and the second gate structure comprises a high-k gate dielectric layer having a k value greater than about 7.0, and the second gate structure is formed by a replacement gate process.
8 . The method of claim 7 , wherein forming the second gate structure comprises:
depositing a second gate dielectric layer on the semiconductor substrate;
depositing an inner gate electrode layer on the second gate dielectric layer;
depositing a ferroelectric layer over the inner gate electrode layer; and
depositing a top gate electrode layer over the ferroelectric layer.
9 . The method of claim 8 , wherein forming the second gate structure further comprising:
forming a work function metal layer between the ferroelectric layer and the top gate electrode layer.
10 . The method of claim 8 , wherein the second gate dielectric layer comprises the high-k dielectric material.
11 . The method of claim 7 , wherein the second gate structure includes a negative capacitance device.
12 . The method of claim 7 , further comprising forming a third gate structure on the substrate, wherein the third gate structure comprises the first gate dielectric layer and the first gate electrode layer.
13 . The method of claim 7 , further comprising forming a third gate structure on the substrate, wherein the third gate structure comprises a ferroelectric layer.
14 . A method, comprising:
forming an image sensing device comprising:
a photodetector comprising a first pinned layer and a second pinned layer;
a transfer transistor comprising a transfer gate overlapping with a portion of the photodetector, wherein the transfer gate includes a first group of material layers;
a source-follower transistor comprising a source-follower gate;
a reset transistor comprising a reset gate; and
a select transistor comprising a select gate, wherein at least one of the source-follower gate, the reset gate, and the select gate includes a second group of material layers different from the first group of material layers, wherein at least one of the transfer gate, the source-follower gate, the reset gate and the select gate is fabricated by a replacement gate process.
15 . The method of claim 14 , wherein the second group of material layers comprises:
a high-k gate dielectric layer; and
a metallic gate electrode layer.
16 . The method of claim 15 , wherein the second group of material layers further comprises:
a ferroelectric layer disposed between the high-k gate dielectric layer and the metallic gate electrode layer.
17 . The method of claim 16 , wherein the second group of material layers further comprises:
a conductive layer disposed between the high-k gate dielectric layer and the ferroelectric layer.
18 . The method of claim 16 , wherein the first group of material layers comprises a polycrystalline silicon layer.
19 . The method of claim 14 , wherein at least one of the transfer gate, the source-follower gate, the reset gate and the select gate includes a negative capacitance device.
20 . The method of claim 15 , wherein the high-k dielectric layer has a k-value greater than about 7.0.