Epitaxial semiconductor liner for enhancing uniformity of a charged layer in a deep trench and methods of forming the same
View Patent ↗Photodetectors, transistors, and metal interconnect structures may be formed on a front side of the semiconductor substrate. A trench is formed through a backside surface of the semiconductor substrate toward the front side by an anisotropic etch process, which provides a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm. A single crystalline semiconductor liner is deposited by performing an epitaxial growth process at a growth temperature less than 500 degrees Celsius on the vertical or tapered surface of the trench. A physically exposed side surface of the single crystalline semiconductor liner may have a second root-mean-square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner having a uniform thickness may be formed on the physically exposed side surface to provide a uniform negatively charged film, which may be advantageously used to reduce dark current and white pixels.
1 . A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate that contains a substrate semiconductor layer which includes a first single crystalline semiconductor material;
forming a trench in the substrate semiconductor layer, wherein a sidewall of the trench comprises a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm;
forming a single crystalline semiconductor liner including a second single crystalline semiconductor material by performing an epitaxial growth process on the vertical or tapered surface of the trench, wherein the single crystalline semiconductor liner contains a vertically-extending portion that has a first side surface that contacts the vertical or tapered surface on a first side and has a second side surface which has a second root-mean-square surface roughness which is less than 0.5 nm; and
forming at least one dielectric metal oxide liner on the second side surface of the single crystalline semiconductor liner.
2 . The method of claim 1 , wherein the epitaxial growth process is performed at a growth temperature less than 500 degrees Celsius.
3 . The method of claim 1 , wherein the epitaxial growth process uses a silicon-containing precursor gas selected from silane and disilane.
4 . The method of claim 1 , wherein the single crystalline semiconductor liner has an average thickness in a range from 1.5 nm to 10 nm.
5 . The method of claim 1 , wherein the first root-mean-square surface roughness is at least three times the second root-mean-square surface roughness.
6 . The method of claim 1 , wherein:
the method comprises forming transistors, interconnect-level dielectric layers, and metal interconnect structures on a front side of the semiconductor substrate; and
the trench is formed through a backside surface of the semiconductor substrate toward the front side of the semiconductor substrate.
7 . The method of claim 6 , further comprising:
attaching a carrier substrate to the interconnect-level dielectric layers; and
thinning the semiconductor substrate after attaching the carrier substrate, wherein the trench is formed after formation of the metal interconnect structures.
8 . The method of claim 6 , further comprising:
forming photodetectors and sensing circuits for photodetectors on the front side of the semiconductor substrate; and
forming a grid structure overlying the backside surface of the semiconductor substrate.
9 . The method of claim 8 , further comprising:
forming an array of color filters over the grid structure; and
forming an array of lenses over the array of color filters.
10 . The method of claim 6 , further comprising:
forming shallow trench isolation structures in the semiconductor substrate between the transistors directly on the front side, wherein the trench comprises a deep trench extending through the semiconductor substrate to one of the shallow trench isolation structures and having a depth in a range from 1.5 microns to 10 microns; and
depositing a dielectric isolation layer in a remaining volume of the deep trench on the at least one dielectric metal oxide liner.
11 . The method of claim 10 , wherein:
the at least one dielectric metal oxide liner comprises at least one oxygen-rich dielectric metal oxide material and having a net negative charge; and
portions of the at least one dielectric metal oxide liner and the dielectric isolation layer in the deep trench constitutes a dielectric isolation structure.
12 . The method of claim 1 , wherein:
more than 50% of an entire surface area of the vertical or tapered surface comprises surface segments that do not contain faceted surfaces of the first single crystalline semiconductor material; and
more than 50% of an entire surface area of the second side surface of the second single crystalline semiconductor material comprises surface segments that are faceted surfaces of the second single crystalline semiconductor material.
13 . A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate that contains a substrate semiconductor layer which includes a first single crystalline semiconductor material;
forming a trench in the substrate semiconductor layer, wherein a sidewall of the trench comprises a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm;
performing an epitaxial growth process that grows a single crystalline semiconductor liner including a second single crystalline semiconductor material on the vertical or tapered surface of the trench, wherein the single crystalline semiconductor liner contains a vertically-extending portion that has a first side surface that contacts the vertical or tapered surface on a first side and has a second side surface which has a second root-mean-square surface roughness which is less than 0 . 5 nm, wherein a duration of the epitaxial growth process is selected such that a thickness of the single crystalline semiconductor liner is in a range from 1.5 nm to 10 nm; and
depositing at least one dielectric metal oxide liner on the second side surface of the single crystalline semiconductor liner.
14 . The method of claim 13 , wherein:
the trench is formed by performing an anisotropic etch process that employs an etch mask and anisotropically etches an unmasked portion of the substrate semiconductor layer; and
a depth of the trench is in a range from 1 micron to 10 microns.
15 . The method of claim 13 , wherein:
more than 50% of an entire surface area of the vertical or tapered surface comprises surface segments that do not contain faceted surfaces of the first single crystalline semiconductor material; and
more than 50% of an entire surface area of the second side surface of the second single crystalline semiconductor material comprises surface segments that are faceted surfaces of the second single crystalline semiconductor material.
16 . The method of claim 13 , wherein the at least one dielectric metal oxide liner comprises an aluminum oxide layer contacting the single crystalline semiconductor liner and having a thickness in a range from 0.8 nm to 1.6 nm, and having a root-mean-square thickness variation less than 0.1 nm.
17 . A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate that contains a substrate semiconductor layer which includes a first single crystalline semiconductor material;
forming a trench in the substrate semiconductor layer, wherein a sidewall of the trench comprises a vertical or tapered surface;
forming a single crystalline semiconductor liner including a second single crystalline semiconductor material by performing an epitaxial growth process on the vertical or tapered surface of the trench, wherein the epitaxial growth process is performed at a growth temperature less than 500 degrees Celsius;
forming at least one dielectric metal oxide liner on a side surface of the single crystalline semiconductor liner, wherein the at least dielectric metal oxide liner comprises at least one oxygen-rich dielectric metal oxide material having a net negative charge, and the net negative charge has an areal density from 5.0×10 9 electrons per cm 2 to 1.0×10 14 electrons per cm 2 ; and
forming a silicon oxide material portion on a surface of the at least one dielectric metal oxide liner.
18 . The method of claim 17 , wherein:
a sidewall of the trench comprises a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm; and
the single crystalline semiconductor liner contains a vertically-extending portion that has an additional side surface that contacts the vertical or tapered surface on a first side; and
the side surface of the single crystalline semiconductor liner has a second root-mean-square surface roughness which is less than 0.5 nm.
19 . The method of claim 17 , wherein the epitaxial growth process uses a silicon-containing precursor gas selected from silane and disilane.
20 . The method of claim 17 , wherein the single crystalline semiconductor liner has an average thickness in a range from 1.5 nm to 10 nm.