IP Library Granted Patent US 12677538
Granted Patent B2
US 12677538 · App. 18/079,115 · Granted Jul 7, 2026

Display device comprising a metal oxide pattern and method for manufacturing the same

Inventors: Sangwoo Sohn (Yongin-si, KR); Yeon Keon Moon (Hwaseong-si, KR); Eun Hyun Kim (Suwon-si, KR); Seungho Yang (Hwaseong-si, KR); Jun Hyung Lim (Seoul, KR); Hyunjun Jeong (Seoul, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/1213H10D30/6755H10K59/1201H10K71/00
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Quick Facts
Patent No.
US 12677538
App. No.
18/079,115
Granted
Jul 7, 2026
Kind
B2
Abstract

A display device includes insulating layers, a light-emitting element, and a pixel circuit electrically connected to the light-emitting element. The pixel circuit includes a first transistor. The first transistor includes a metal oxide semiconductor pattern including a source region, a drain region and a channel region disposed between the source region and the drain region, a first gate disposed on the metal oxide semiconductor pattern and overlapping the channel region in a plan view, and a metal oxide pattern disposed on the first gate.

Claims (50)

1 . A display device comprising:

insulating layers;

a light-emitting element; and

a pixel circuit electrically connected to the light-emitting element, wherein

the pixel circuit comprises a first transistor, and

the first transistor comprises:

a metal oxide semiconductor pattern including a source region, a drain region and a channel region disposed between the source region and the drain region,

a first gate disposed on the metal oxide semiconductor pattern, and overlapping the channel region in a plan view, and

a metal oxide pattern disposed on the first gate, wherein

the display device further comprises a connection electrode connected to the source region and to the metal oxide pattern.

2 . The display device of claim 1 , wherein the insulating layers comprise:

a first insulating layer disposed between the channel region and the first gate;

a second insulating layer having a first portion disposed between the first gate and the metal oxide pattern, a second portion disposed on the source region, and a third portion disposed on the drain region; and

a third insulating layer disposed on the second insulating layer and the metal oxide pattern.

3 . The display device of claim 2 , wherein

the first insulating layer comprises a first silicon oxide layer,

the second insulating layer comprises a second silicon oxide layer or a first silicon oxynitride layer, and

the third insulating layer comprises a second silicon oxynitride layer and a first silicon nitride layer disposed on the second silicon oxynitride layer.

4 . The display device of claim 2 , wherein the second insulating layer covers a side surface of the first insulating layer.

5 . The display device of claim 1 , wherein the metal oxide pattern electrically contacts an upper surface of the first gate.

6 . The display device of claim 1 , wherein the pixel circuit further comprises a conductive pattern disposed on the metal oxide pattern.

7 . The display device of claim 6 , wherein

a corresponding insulating layer among the insulating layers is disposed between the first gate and the conductive pattern, and

the first gate and the conductive pattern define a capacitor.

8 . The display device of claim 1 , wherein the first transistor is configured to control a driving current of the light-emitting element based on a charged capacitance of a capacitor defined by the first gate and a conductive pattern on the metal oxide pattern.

9 . The display device of claim 1 , wherein

the pixel circuit further comprises a second transistor,

the second transistor comprises a second metal oxide semiconductor pattern, and

the second transistor is configured to supply a data voltage to a capacitor defined by the first gate and a conductive pattern on the metal oxide pattern.

10 . The display device of claim 1 , wherein an edge of the metal oxide pattern is aligned with an edge of a conductive pattern on the metal oxide pattern.

11 . The display device of claim 1 , wherein the channel region has a length of about 3 μm or less.

12 . The display device of claim 1 , wherein the first transistor further comprises a second gate electrically connected to the first gate and disposed below the metal oxide semiconductor pattern.

13 . The display device of claim 1 , wherein the metal oxide pattern comprises at least one of indium (In), tin (Sn), zinc (Zn), gallium (Ga), magnesium (Mg), hafnium (Hf), and titanium (Ti).

14 . The display device of claim 13 , wherein the metal oxide pattern comprises at least one of tin (Sn), magnesium (Mg), and hafnium (Hf).

15 . The display device of claim 1 , wherein the metal oxide pattern has a thickness in a range of about 100 Å to about 300 Å.

16 . The display device of claim 1 , wherein the connection electrode includes:

a first contact directly connected to the source region;

a second contact connected to the metal oxide pattern; and

a metal runner directly connected to an upper surface of the first contact and to an upper surface of the second contact.

17 . The display device of claim 16 , further comprising:

a first conductive pattern;

a second conductive pattern on the first conductive pattern; and

a dielectric pattern between the first conductive pattern and the second conductive pattern, wherein

the connection electrode further includes a third contact connected to the first conductive pattern, an upper surface of the third contact directly connected to the metal runner.

18 . The display device of claim 17 , further comprising:

a conformal insulating layer on the second conductive pattern and between the metal oxide pattern and the first gate; and

an interlayer insulating layer directly on an upper surface of the conformal insulating layer.

19 . The display device of claim 1 , further comprising:

a conformal insulating layer between the metal oxide pattern and the first gate,

wherein a thickness of the metal oxide pattern is thinner than a thickness of the conformal insulating layer.