Array substrate and method for manufacturing same, display panel and display device

1 . An array substrate, comprising:

a base substrate and a driving thin-film transistor disposed on the base substrate, wherein

the driving thin-film transistor comprises a first gate, a first insulating layer, a first active layer, a second insulating layer, and a first source/drain electrode which are sequentially laminated on the base substrate, a thickness of the first insulating layer being greater than a thickness of the second insulating layer, and the thickness of the first insulating layer being positively correlated with a subthreshold swing of the driving thin-film transistor;

the driving thin-film transistor further comprises a conductive structure disposed between the second insulating layer and the first source/drain electrode, wherein an orthographic projection of the conductive structure on the base substrate is overlapped with an orthographic projection of the first gate on the base substrate; and the first source/drain electrode comprises a first electrode electrically connected with a power supply and a second electrode electrically connected with a light-emitting unit, the second electrode being electrically connected with the conductive structure; and

the driving thin-film transistor further comprises a fourth insulating layer disposed between the conductive structure and the first source/drain electrode, both the fourth insulating layer and the second insulating layer are provided with a plurality of through holes, the first electrode and the second electrode are connected to the first active layer via the trough holes in the fourth insulating layer and the second insulating layer, and the second electrode is further connected to the conductive structure via the through holes in the fourth insulating layer.

2 . The array substrate according to claim 1 , further comprising: a switching thin-film transistor disposed on the base substrate, wherein

the switching thin-film transistor comprises a second active layer, a third insulating layer, a second gate, and a second source/drain electrode which are sequentially laminated on the base substrate, the third insulating layer and the second insulating layer being disposed in a same layer.

3 . The array substrate according to claim 1 , wherein a ratio of the thickness of the first insulating layer to the thickness of the second insulating layer ranges from 1.2 to 5.

4 . The array substrate according to claim 1 , wherein the first active layer comprises a first semiconductor layer and a second semiconductor layer sequentially laminated in a direction away from the base substrate, wherein

a mobility of the first semiconductor layer is greater than a mobility of the second semiconductor layer; and

the second semiconductor layer covers a surface of the first semiconductor layer away from the base substrate.

5 . The array substrate according to claim 4 , wherein

the first semiconductor layer comprises a top surface and a bottom surface which are opposite to each other, and a side surface connecting the top surface and the bottom surface, the bottom surface facing towards the base substrate; and

the second semiconductor layer covers the top surface and the side surface of the first semiconductor layer.

6 . The array substrate according to claim 4 , wherein the mobility of the first semiconductor layer ranges from 20 cm 2 /(V·s) to 100 cm 2 /(V·s) and the mobility of the second semiconductor layer ranges from 5 cm 2 /(V·s) to 30 cm 2 /(V·s).

7 . A method for manufacturing an array substrate, comprising:

acquiring a base substrate;

forming a driving thin-film transistor on the base substrate;

wherein forming the driving thin-film transistor comprises:

sequentially forming a first gate and a first insulating layer which are laminated;

forming a first active layer on the first insulating layer; and

sequentially forming a second insulating layer and a first source/drain electrode on the base substrate on which the first active layer is formed;

wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer, and the thickness of the first insulating layer is positively correlated with a subthreshold swing of the driving thin-film transistor;

the driving thin-film transistor further comprises a conductive structure disposed between the second insulating layer and the first source/drain electrode, wherein an orthographic projection of the conductive structure on the base substrate is overlapped with an orthographic projection of the first gate on the base substrate; and the first source/drain electrode comprises a first electrode electrically connected with a power supply and a second electrode electrically connected with a light-emitting unit, the second electrode being electrically connected with the conductive structure; and

the driving thin-film transistor further comprises a fourth insulating layer disposed between the conductive structure and the first source/drain electrode, both the fourth insulating layer and the second insulating layer are provided with a plurality of through holes, the first electrode and the second electrode are connected to the first active layer via the trough holes in the fourth insulating layer and the second insulating layer, and the second electrode is further connected to the conductive structure via the through holes in the fourth insulating layer.

8 . The method according to claim 7 , wherein forming the first active layer on the first insulating layer comprises:

forming the first active layer on the base substrate on which the first insulating layer has formed in an environment with an oxygen concentration greater than or equal to 20%.

9 . The method according to claim 7 , wherein forming the first active layer on the first insulating layer comprises:

sequentially forming a first semiconductor material layer and a second semiconductor material layer on the base substrate on which the first insulating layer has formed; and

performing a one-time patterning process on the first semiconductor material layer and the second semiconductor material layer to form a first semiconductor layer and a second semiconductor layer;

wherein the second semiconductor layer covers a surface of the first semiconductor layer away from the base substrate.

10 . A display panel, comprising an array substrate, wherein the array substrate comprises:

a base substrate and a driving thin-film transistor disposed on the base substrate, wherein

the driving thin-film transistor comprises a first gate, a first insulating layer, a first active layer, a second insulating layer, and a first source/drain electrode which are sequentially laminated on the base substrate, a thickness of the first insulating layer being greater than a thickness of the second insulating layer, and the thickness of the first insulating layer being positively correlated with a subthreshold swing of the driving thin-film transistor;

the driving thin-film transistor further comprises a conductive structure disposed between the second insulating layer and the first source/drain electrode, wherein an orthographic projection of the conductive structure on the base substrate is overlapped with an orthographic projection of the first gate on the base substrate; and the first source/drain electrode comprises a first electrode electrically connected with a power supply and a second electrode electrically connected with a light-emitting unit, the second electrode being electrically connected with the conductive structure; and

the driving thin-film transistor further comprises a fourth insulating layer disposed between the conductive structure and the first source/drain electrode, both the fourth insulating layer and the second insulating layer are provided with a plurality of through holes, the first electrode and the second electrode are connected to the first active layer via the trough holes in the fourth insulating layer and the second insulating layer, and the second electrode is further connected to the conductive structure via the through holes in the fourth insulating layer.

11 . A display device, comprising the display panel as defined in claim 10 .

12 . The display panel according to claim 10 , wherein the array substrate further comprises: a switching thin-film transistor disposed on the base substrate, wherein

the switching thin-film transistor comprises a second active layer, a third insulating layer, a second gate, and a second source/drain electrode which are sequentially laminated on the base substrate, the third insulating layer and the second insulating layer being disposed in a same layer.

13 . The display panel according to claim 10 , wherein a ratio of the thickness of the first insulating layer to the thickness of the second insulating layer ranges from 1.2 to 5.

14 . The display panel according to claim 10 , wherein the first active layer comprises a first semiconductor layer and a second semiconductor layer sequentially laminated in a direction away from the base substrate, wherein

a mobility of the first semiconductor layer is greater than a mobility of the second semiconductor layer.

15 . The display panel according to claim 14 , wherein the second semiconductor layer covers a surface of the first semiconductor layer away from the base substrate.

16 . The display panel according to claim 14 , wherein

the first semiconductor layer comprises a top surface and a bottom surface which are opposite to each other, and a side surface connecting the top surface and the bottom surface, the bottom surface facing towards the base substrate; and

the second semiconductor layer covers the top surface and the side surface of the first semiconductor layer.

17 . The display panel according to claim 14 , wherein the mobility of the first semiconductor layer ranges from 20 cm 2 /(V·s) to 100 cm 2 /(V·s) and the mobility of the second semiconductor layer ranges from 5 cm 2 /(V·s) to 30 cm 2 /(V·s).