Display panel and display device
The present disclosure relates to display panels and display devices that are capable of simplifying a manufacturing process and more specifically to: a display area including a first optical area including a central area and a bezel area located outside of the central area and a normal area located outside of the first optical area. A plurality of light emitting elements disposed in the central area and a plurality of light emitting elements and a plurality of transistors including a plurality of source-drain electrode patterns are disposed in the bezel area. There is a connection pattern contacting a first source-drain electrode pattern in the bezel area and extending to a portion of the central area. In one embodiment, one of the plurality of source-drain electrode patterns and the at least one connection pattern are disposed on a same layer and include different materials.
1 . A display device comprising:
a display panel comprising a first area, a second area outside of the first area, and a third area surrounding the first area and the second area;
wherein the display panel comprises:
a first plurality of light emitting elements disposed in the first area;
a second plurality of light emitting elements and a first plurality of transistors disposed in the second area; and
a third plurality of light emitting elements and a second plurality of transistors disposed in the third area, and
wherein a number of the first plurality of light emitting elements is different from a number of the third plurality of light emitting elements, and a number of the first plurality of transistors is different from a number of the second plurality of transistors
wherein the display panel further comprises a plurality of connection patterns comprising at least one first connection pattern and at least one second connection pattern extending from the second area to a portion of the first area, and
wherein the at least one first connection pattern is electrically connected to at least one first anode electrode among anode electrodes of the first plurality of light emitting elements such that the at least one first connection pattern is overlapped with at least one second anode electrode electrically connected to the at least one second connection pattern among the anode electrodes and is not of at least one of the first plurality of light emitting elements electrically connected to the at least one second anode electrode within the first area in a cross-sectional view.
2 . The display device of claim 1 , wherein the display panel further comprises:
an insulating layer disposed on the at least one first connection pattern,
wherein the at least one second connection pattern is disposed on the insulating layer.
3 . The display device of claim 2 , wherein the at least one first connection pattern and the at least one second connection pattern overlap with each other in an area adjacent to the second area within the first area.
4 . The display device of claim 2 , wherein the second anode electrode, the insulating layer, and at least one of the at least one first connection pattern and the at least one second connection pattern overlap with each other in the cross-sectional view.
5 . The display device of claim 1 , wherein each of the first plurality of light emitting elements and the second plurality of light emitting elements comprises an anode electrode, a cathode electrode, and an emission layer located between the anode electrode and the cathode electrode, and each of the first plurality of transistors comprises a gate electrode, a source electrode, and a drain electrode.
6 . The display device of claim 5 , wherein the at least one first connection pattern or the at least one second connection pattern is connected to the source electrode or the drain electrode.
7 . The display device of claim 1 , wherein each of the first plurality of transistors or the second plurality of transistors comprises a gate electrode, a source electrode, and a drain electrode, and
wherein the display panel further comprises a capacitor comprising a first electrode including a same material as the gate electrode and a second electrode overlapping with the first electrode.
8 . The display device of claim 7 , wherein a first metal layer including a same metal as the second electrode of the capacitor overlaps with the source electrode or the drain electrode.
9 . The display device of claim 7 , wherein at least one second metal layer is disposed in the first area in a same layer as the source electrode or the drain electrode.
10 . The display device of claim 7 , wherein each of the first plurality of light emitting elements and the second plurality of light emitting elements comprises an anode electrode, a cathode electrode, and an emission layer located between the anode electrode and the cathode electrode, and at least one of the second metal layer overlaps with the anode electrode.
11 . The display device of claim 7 , wherein the display panel further comprises:
a substrate on which the first area, the second area, and the third area are defined; and
a metal pattern disposed over the substrate, and
wherein the metal pattern overlaps with a portion of at least one transistor among the first plurality of transistors or the second plurality of transistors.
12 . The display device of claim 11 , wherein the metal pattern overlaps with one or more source-drain electrode pattern of the at least one transistor.
13 . The display device of claim 1 , wherein the display panel further comprises:
an encapsulation layer disposed on at least one of the first plurality of light emitting elements, the second plurality of light emitting elements, and the third plurality of light emitting elements;
a touch buffer layer disposed on the encapsulation layer; and
a touch sensor disposed on the touch buffer layer.
14 . The display device of claim 13 , wherein the touch sensor is disposed in the at least a portion of the first area.
15 . A display device comprising:
a display panel comprising a first area, a second area outside of the first area, and a third area surrounding the first area and the second area;
wherein the display panel comprises:
a first plurality of light emitting elements disposed in the first area;
a second plurality of light emitting elements and a first plurality of transistors disposed in the second area; and
a third plurality of light emitting elements and a second plurality of transistors disposed in the third area, and
wherein a number of the first plurality of light emitting elements is different from a number of the third plurality of light emitting elements, and a number of the first plurality of transistors is different from a number of the second plurality of transistors,
wherein the display panel further comprises at least one insulating layer disposed between at least one of the first plurality of light emitting elements, the second plurality of light emitting elements, and the third plurality of light emitting elements and at least one of the first plurality of transistors and the second plurality of transistors, and
wherein a bank is disposed on the at least one insulating layer and comprises a plurality of spacers.
16 . The display device of claim 15 , wherein each of the plurality of spacers overlaps with respective portions of adjacent anode electrodes.
17 . The display device of claim 15 , wherein at least one spacer among the plurality of spacers is located between the first area and the second area.
18 . The display device of claim 15 , wherein at least one spacer among the plurality of spacers is located between the second area and the third area.
19 . The display device of claim 15 , wherein at least one spacer disposed in the first area among the plurality of spacers has a shape different from at least one spacer disposed in the second or third area among the plurality of spacers.
20 . The display device of claim 15 , wherein the display panel further comprises a passivation layer disposed between the at least one insulating layer and the at least one of the first plurality of transistors and the second plurality of transistors, and disposed along respective upper portions of source-drain electrode patterns of the at least one of the first plurality of transistors and the second plurality of transistors.