Quantum chip and fabrication method therefor
Disclosed are a quantum chip and a fabrication method therefor. The quantum chip includes a base substrate on which signal transmission lines are formed; and at least one insulating substrate located on the base substrate, where a qubit and a through hole penetrating through the insulating substrate are formed on the insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the qubit, respectively.
1 . A quantum chip, comprising:
a base substrate on which signal transmission lines are formed; and
at least one insulating substrate, wherein the insulating substrate is located on the base substrate, a qubit and a through hole penetrating through the insulating substrate are formed on the insulating substrate, a metal piece is formed in the through hole; and two ends of the metal piece are electrically connected to the signal transmission lines and the qubit, respectively; and
an isolation layer located between the base substrate and the insulating substrate, wherein the through hole penetrates through the isolation layer, and wherein the isolation layer comprises:
an insulating isolation layer located on the base substrate, wherein the insulating isolation layer covers the signal transmission lines, and the through hole penetrates through the insulating isolation layer; and
a metal isolation layer located on the insulating isolation layer, wherein a via hole for forming a mesh is formed on the metal isolation layer, and the through hole is located in the via hole for forming a mesh.
2 . The quantum chip according to claim 1 , wherein the signal transmission lines comprise:
a qubit control signal line coupled to the qubit, wherein the qubit control signal line is configured to control information of the qubit;
a qubit microwave resonant cavity coupled to the qubit, wherein the qubit microwave resonant cavity is configured to read information of the qubit; and
a qubit read signal line coupled to the qubit microwave resonant cavity, wherein the qubit read signal line is configured to read information output by the qubit microwave resonant cavity.
3 . The quantum chip according to claim 2 , wherein the qubit microwave resonant cavity comprises a coplanar waveguide transmission line.
4 . The quantum chip according to claim 1 , wherein an aperture of the via hole for forming a mesh is greater than an aperture of the through hole, and the via hole for forming a mesh and the through hole are coaxially arranged.
5 . The quantum chip according to claim 1 , wherein the at least one insulating substrate comprises:
a first insulating substrate located on the base substrate, wherein a first qubit and a through hole penetrating through the first insulating substrate are formed on the first insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the first qubit, respectively; and
a second insulating substrate located on the first insulating substrate, wherein a second qubit and a through hole penetrating through both the second insulating substrate and the first insulating substrate are formed on the second insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the second qubit, respectively.
6 . The quantum chip according to claim 1 , wherein the metal piece fully fills the through hole and is configured to implement an electrical connection between the base substrate and a circuit structure on the insulating substrate.
7 . The quantum chip according to claim 1 , wherein the metal piece is a metal film formed on an inner surface of the through hole.
8 . The quantum chip according to claim 1 , wherein the metal piece is formed in a columnar shape inside the through hole.
9 . The quantum chip according to claim 1 , wherein a capacitor for connecting the qubit and the metal piece is formed on the insulating substrate.
10 . The quantum chip according to claim 9 , wherein adjacent qubits are coupled with each other through the capacitor.
11 . The quantum chip according to claim 9 , wherein when the quantum chip is a superconducting quantum chip, the qubit comprises a loop superconducting circuit and the capacitor, and the metal piece connected to the qubit and located in the through hole is connected to the loop superconducting circuit.
12 . The quantum chip according to claim 11 , wherein the loop superconducting circuit comprises at least two superconducting Josephson junctions connected in parallel.
13 . The quantum chip according to claim 1 , wherein the quantum chip further comprises signal terminals, and the signal terminals are formed on a side surface of the base substrate and electrically connected to the signal transmission lines in a one-to-one correspondence manner.
14 . The quantum chip according to claim 1 , wherein a material of the insulating isolation layer comprises one of silicon dioxide, amorphous silicon and Teflon.
15 . The quantum chip according to claim 1 , wherein the qubit is at least paired to form at least two control signal line through holes and one read signal line through hole.
16 . A fabrication method for a quantum chip, comprising:
providing a base substrate on which signal transmission lines are formed;
forming at least one insulating substrate on the base substrate, wherein a qubit and a through hole penetrating through the insulating substrate are formed on the insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the qubit, respectively; and
forming an isolation layer between the base substrate and the insulating substrate, wherein the through hole penetrates through the isolation layer, and wherein the isolation layer comprises:
an insulating isolation layer located on the base substrate, wherein the insulating isolation layer covers the signal transmission lines, and the through hole penetrates through the insulating isolation layer; and
a metal isolation layer located on the insulating isolation layer, wherein a via hole for forming a mesh is formed on the metal isolation layer, and the through hole is located in the via hole for forming a mesh.
17 . The fabrication method according to claim 16 , wherein the step of forming at least one insulating substrate on the base substrate, wherein a qubit and a through hole penetrating through the insulating substrate are formed on the insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the qubit, respectively comprises:
forming a first insulating substrate on the base substrate, and forming a first qubit and a through hole penetrating through the first insulating substrate on the first insulating substrate, wherein a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the first qubit, respectively; and
forming a second insulating substrate on the first insulating substrate, and forming a second qubit and a through hole penetrating through both the second insulating substrate and the first insulating substrate on the second insulating substrate, wherein a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the second qubit, respectively.