IP Library › Granted Patent US 12677605
Granted Patent B2
US 12677605 · App. 18/065,816 · Granted Jul 7, 2026

Reusable templates for semiconductor design and fabrication

Inventors: Gabriel H. Loh (Bellevue, WA); Todd David Basso (Boxborough, MA); Steven Tu (Austin, TX); Joshua A. Hort (Boxborough, MA); Chia-Ken Leong (Santa Clara, CA); Benjamin Beker (Austin, TX); Anwar P. Kashem (Boxborough, MA)
Assignee: ADVANCED MICRO DEVICES, INC.
H10P14/40H10P72/74
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Quick Facts
Patent No.
US 12677605
App. No.
18/065,816
Granted
Jul 7, 2026
Kind
B2
Abstract

A substrate includes a location for coupling one or more chiplets to the substrate. The location has dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the location. Additionally, the location includes an interface region having connections for one or more die-to-die interfaces of the one or more chiplets and a power region that includes a power interface having connections for the one or more chiplets.

Claims (25)

1 . A substrate comprising:

a first location for coupling one or more chiplets to the substrate, the first location having dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the first location, the first location including an interface region and a power region, the interface region including connections for one or more die-to-die interfaces and the power region including a power interface having connections for the one or more chiplets;

a second location for coupling one or more additional chiplets to the substrate, the second location having dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the second location, the second location including an interface region and a power region, the interface region including connections for one or more die-to-die interfaces and the power region including a power interface having connections for the one or more additional chiplets; and

connections within the substrate coupling the interface region in the first location to the interface region in the second location.

2 . The substrate of claim 1 , wherein each of the first location and the second location is configured to receive a plurality of different chiplets having combined dimensions that do not exceed the dimensions of the respective location.

3 . The substrate of claim 1 , wherein each of the first location and the second location is configured to receive a plurality of different chiplets having different widths and a combination of the different widths does not exceed a width of the respective location.

4 . The substrate of claim 1 , wherein each of the first location and the second location is configured to receive a plurality of different chiplets having different lengths and a combination of the different lengths does not exceed a length of the respective location.

5 . The substrate of claim 1 , wherein each of the first location and the second location includes a sideband region, and wherein the substrate includes connections between the sideband region of the first location and the sideband region of the second location for a sideband interface between a chiplet in the first location and another chiplet in the second location, the sideband interface augmenting a die-to-die interface.

6 . The substrate of claim 1 , wherein the first location includes an external connection region including connections coupling a chiplet to one or more components external to a semiconductor assembly including the substrate, and the substrate includes a connection pathway from a connection in the external connection region to an outside connection.

7 . A semiconductor assembly comprising:

a substrate comprising:

a first location for coupling one or more chiplets to the substrate, the first location having dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the first location, the first location including an interface region and a power region, the interface region including connections for one or more die-to-die interfaces and the power region including a power interface having connections for the one or more chiplets;

a second location for coupling one or more additional chiplets to the substrate, the second location having dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the second location, the second location including an interface region and a power region, the interface region including connections for one or more die-to-die interfaces and the power region including a power interface having connections for the one or more additional chiplets;

connections within the substrate coupling the interface region in the first location to the interface region in the second location; and

at least one chiplet coupled to at least a subset of the connections in the interface region of the first location and to a subset of the connections in the power region of the first location, the at least one chiplet having dimensions that do not exceed dimensions of the first location.

8 . The semiconductor assembly of claim 7 , further comprising:

at least one additional chiplet coupled to the second location.

9 . The semiconductor assembly of claim 7 , wherein each of the first location and the second location is configured to receive a plurality of different chiplets having combined dimensions that do not exceed the dimensions of the respective location.

10 . The semiconductor assembly of claim 7 , wherein each of the first location and the second location is configured to receive a plurality of different chiplets having different widths and a combination of the different widths does not exceed a width of the respective location.

11 . The semiconductor assembly of claim 7 , wherein each of the first location and the second location is configured to receive a plurality of different chiplets having a length and a combination of the lengths does not exceed a length of the respective location.

12 . The semiconductor assembly of claim 11 , wherein each of the plurality of different chiplets have a different length.

13 . The semiconductor assembly of claim 7 , wherein a subset of the connections in the power region of the first location are not coupled to a chiplet.

14 . The semiconductor assembly of claim 7 , wherein a subset of connections in the interface region of the second location on the substrate are not coupled to a chiplet.

15 . The semiconductor assembly of claim 7 , wherein each of the first location and the second location includes a sideband region, and wherein the substrate includes connections between the sideband region of the first location and the sideband region of the second location for a sideband interface between a chiplet in the first location and another chiplet in the second location, the sideband interface augmenting a die-to-die interface.

16 . The semiconductor assembly of claim 7 , wherein the first location includes an external connection region including connections coupling a chiplet to one or more components external to the semiconductor assembly including the substrate, and wherein the substrate includes a connection pathway from a connection in the external connection region to an outside connection.