Electrical characterization of misalignment in integrated circuit manufacturing

Inventors: Hao Yang (Allen, TX); John K. Arch (Richardson, TX)

Assignee: TEXAS INSTRUMENTS INCORPORATED

H01L21/67259 H10D62/115

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Quick Facts

Patent No.: US 12677628
App. No.: 18/175,718
Granted: Jul 7, 2026
Kind: B2

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Abstract

A method includes performing a fabrication process that fabricates a wafer having an upper region and unit areas arranged in rows along a first direction and columns along an orthogonal second direction and respective scribe streets between adjacent unit areas to: form first and second electrical components on or in the upper region in respective unit areas or scribe streets, the first and second electrical components spaced apart from one another and including structural features with different respective first and second spacing distances along the first direction.

Claims (32)

1 . An electronic device, comprising:

a device die including a semiconductor substrate having a side that extends in a plane of orthogonal first and second directions;

a first rotationally asymmetric electrical component including first and second structural features formed in or over the semiconductor substrate, the first structural feature in the first electrical component spaced apart from the second structural feature in the first electrical component by a first spacing distance; and

a second rotationally asymmetric electrical component nominally identical to the first electrical component and including the first and the second structural features formed in or over the semiconductor substrate, the first structural feature in the second electrical component spaced apart from the second structural feature in the second electrical component by the first spacing distance, the second electrical component rotated with respect to the first electrical component.

2 . The electronic device of claim 1 , wherein the first and second electrical components are transistors and the first spacing distance is gate polysilicon to lightly doped drain spacing distances along the first direction.

3 . The electronic device of claim 1 , wherein the first and second electrical components are transistors and the first spacing distance is gate polysilicon to source/drain contact spacing distances.

4 . The electronic device of claim 1 , wherein the first and second electrical components are transistors and the first spacing distance is shallow well edge to moat edge spacing distances.

5 . The electronic device of claim 1 , wherein the first and second electrical components are transistors and the first spacing distance is source/drain contact to moat edge spacing distances.

6 . The electronic device of claim 1 , wherein the first and second electrical components are located in a scribe street of the device die.

7 . A method, comprising:

forming an integrated circuit over and extending into a semiconductor substrate and including a device active region surrounded by a scribe seal;

forming a first rotationally asymmetric electrical component including first and second structural features in or over the semiconductor substrate, the first structural feature in the first electrical component spaced apart from the second structural feature in the first electrical component by a first spacing distance; and

forming a second rotationally asymmetric electrical component nominally identical to the first electrical component and including the first and the second structural features formed in or over the semiconductor substrate, the first structural feature in the second electrical component spaced apart from the second structural feature in the second electrical component by the first spacing distance, the second electrical component rotated with respect to the first electrical component.

8 . The method of claim 7 , wherein the first and second electrical components are located in the device active region.

9 . The electronic device of claim 1 , comprising:

a third electrical component including the first and the second structural features formed in or over the semiconductor substrate, the first structural feature in the third electrical component spaced apart from the second structural feature in the third electrical component by a second spacing distance different from the first spacing distance; and

a fourth electrical component nominally identical to the third electrical component and including the first and the second structural features formed in or over the semiconductor substrate, the first structural feature in the third electrical component spaced apart from the second structural feature in the third electrical component by the second spacing distance, the fourth electrical component rotated with respect to the third electrical component.

10 . The electronic device of claim 1 , wherein the second electrical component is rotated 180° with respect to the first electrical component.

11 . The electronic device of claim 1 , wherein the first electrical component is configured to be biased in the first direction, and the second electrical component is configured to be biased in a third direction opposite the first direction.

12 . The method of claim 7 , wherein the first and second electrical components are transistors and the first spacing distance is gate polysilicon to lightly doped drain spacing distance.

13 . The method of claim 7 , wherein the first and second electrical components are transistors and the first spacing distance is gate polysilicon to source/drain contact spacing distances.

14 . The method of claim 7 , wherein the first and second electrical components are transistors and the first spacing distance is shallow well edge to moat edge spacing distances.

15 . The method of claim 7 , wherein the first and second electrical components are transistors and the first spacing distance is source/drain contact to moat edge spacing distances.

16 . An electronic device, comprising:

a device die including a semiconductor substrate;

a first electrical component including first and second structural features formed in or over the semiconductor substrate, the first structural feature in the first electrical component spaced apart from the second structural feature in the first electrical component by a first spacing distance, the first electrical component having first terminals spaced apart along an axis; and

a second electrical component nominally identical to the first electrical component and including the first and the second structural features formed in or over the semiconductor substrate, the first structural feature in the second electrical component spaced apart from the second structural feature in the second electrical component by the first spacing distance, the second electrical component having second terminals spaced apart along the axis,

wherein the first electrical component is configured to be biased between the first terminals in a first direction along the axis, and the second electrical component is configured to be biased between the second terminals in a second opposite direction along the axis.

17 . The electronic device of claim 16 , comprising:

wherein the third electrical component is configured to be biased between the third terminals in the first direction, and the second electrical component is configured to be biased between the fourth terminals in the second direction.