Semiconductor device
A semiconductor device with a structure in which a plurality of chips are stacked includes: a chip area; a scribe lane at a circumference of the chip area; a dam structure that separates the chip area and the scribe lane; a detection wire that extends from the chip area to the scribe lane by passing through the dam structure; and a detection circuit in the chip area that is electrically connected to the detection wire and is configured to detect a defect in the scribe lane.
1 . A semiconductor device with a structure in which a plurality of chips are stacked, comprising:
a chip area;
a scribe lane at a circumference of the chip area;
a dam structure that separates the chip area and the scribe lane;
a detection wire that extends from the chip area to the scribe lane by passing through the dam structure; and
a detection circuit in the chip area that is electrically connected to the detection wire and is configured to detect a defect in the scribe lane.
2 . The semiconductor device of claim 1 , wherein
the plurality of chips comprise:
a first chip having a first bonding metal pattern, and a second chip on the first chip and including a second bonding metal pattern corresponding to the first bonding metal pattern, and
wherein the first chip and the second chip are bonded together by bonding the first bonding metal pattern and the second bonding metal pattern to each other.
3 . The semiconductor device of claim 2 , wherein
in the scribe lane, the detection wire comprises the first bonding metal pattern and the second bonding metal pattern.
4 . The semiconductor device of claim 3 , wherein
in the scribe lane,
the detection wire comprises first and second detection wire structures on the first and second chips, respectively, and first and second contact plugs that connect the first and second detection wire structures to the first and second bonding metal patterns, respectively.
5 . The semiconductor device of claim 4 , wherein
the dam structure comprises a through hole, and
at least one of the first and second detection wire structures extends from the chip area and is connected to a connection wiring structure passing through the through hole.
6 . The semiconductor device of claim 1 , wherein
the detection wire extending into the scribe lane at least partially surrounds the dam structure in a plan view.
7 . The semiconductor device of claim 1 , wherein
the detection circuit comprises a switch that is configurable to control connection to the detection wire.
8 . The semiconductor device of claim 7 , wherein
detection pads are on one side and the other side of the detection wire, respectively.
9 . The semiconductor device of claim 1 , wherein
the dam structure includes an inner dam adjacent to the chip area and surrounding the chip area in a plan view, and an outer dam spaced parallel to the inner dam and surrounding the inner dam in the plan view, the outer dam being between the inner dam and the scribe lane.
10 . The semiconductor device of claim 9 , wherein
the inner dam comprises a first through portion through which the detection wire passes, and the outer dam comprises a second through portion through which the detection wire extending through the first through portion passes.
11 . The semiconductor device of claim 10 , wherein
the inner dam and the outer dam each have a rectangular ring shape, and
at least one of the first through portion and the second through portion is adjacent to one vertex of the rectangular ring shape.
12 . The semiconductor device of claim 1 , wherein
the detection circuit comprises a plurality of detection circuits,
the detection wire comprises a plurality of detection wires electrically separated from each other, and
the plurality of detection circuits are electrically connected to the plurality of detection wires, respectively.
13 . The semiconductor device of claim 1 , wherein
the dam structure has a square ring shape,
the detection wire comprises a plurality of detection wires passing through each corner side of the dam structure, and
the plurality of detection wires are electrically separated from each other.
14 . A semiconductor device comprising:
a chip area including a detection circuit portion;
a scribe lane at a circumference of the chip area;
at least one dam between the chip area and the scribe lane; and
a detection wire that is electrically connected to the detection circuit portion, and extends from the chip area to the scribe lane by passing through the at least one dam.
15 . The semiconductor device of claim 14 , wherein the at least one dam between the chip area and the scribe lane separates the chip area and the scribe lane,
wherein the detection wire comprises
an extension portion extending along the scribe lane to surround the at least one dam in a plan view, and a connection portion passing through the at least one dam to connect the detection circuit portion and the extension portion.
16 . The semiconductor device of claim 14 , wherein
the detection circuit portion is configured to apply an input signal to the detection wire and is configured to receive an output signal from the detection wire to detect a defect in the scribe lane.
17 . The semiconductor device of claim 16 , wherein
the input signal comprises a pulse, a signal, and/or a DC voltage.
18 . The semiconductor device of claim 14 , wherein
the detection circuit portion comprises a switch that is configurable to cut off an electrical connection with the detection wire, and
the detection wire comprises an input pad configured to apply an input signal and an output pad configured to output an output signal.
19 . The semiconductor device of claim 14 , wherein
the scribe lane comprises a lower structure including a first bonding metal pattern that is combined with an upper structure including a second bonding metal pattern corresponding to the first bonding metal pattern, and
the detection wire comprises the first bonding metal pattern and the second bonding metal pattern.
20 . A semiconductor device bonded with a plurality of wafers, comprising:
a chip area;
a scribe lane at a circumference of the chip area;
a dam structure between the chip area and the scribe lane, and including an inner dam in a form of a first square ring surrounding the chip area in a plan view and an outer dam in a form of a second square ring spaced at a predetermined distance from the inner dam in a direction of the scribe lane;
a detection wire extending from the chip area to the scribe lane through the dam structure; and
a detection circuit portion in the chip area and electrically connected to the detection wire,
wherein the detection circuit portion is configured to apply an input signal to the detection wire and is configured to detect a defect in the scribe lane using an output signal received through the detection wire; and
a first through portion through which the detection wire passes in the inner dam; and
a second through portion through which the detection wire passes in the outer dam,
wherein the first through portion and the second through portion are on opposite corner sides of the first and second square rings, respectively.