Semiconductor package and method of fabricating the same

1 . A semiconductor package, comprising:

a first structure that includes an upper connection pattern;

a second structure that includes a lower connection pattern;

a connection structure that connects the upper connection pattern of the first structure to the lower connection pattern of the second structure; and

a molding layer that surrounds the connection structure,

wherein:

the connection structure includes:

a lower conductor connected to the upper connection pattern of the first structure;

an upper conductor connected to the lower conductor and the lower connection pattern of the second structure; and

a dielectric pattern that at least partially surrounds the upper conductor, and

the dielectric pattern includes:

a first surface in contact with the upper conductor;

a second surface in contact with the lower conductor; and

a third surface having a first portion in contact with the molding layer and a second portion in contact with the lower conductor.

2 . The semiconductor package as claimed in claim 1 , wherein:

the upper conductor includes:

a lower portion in contact with the lower conductor; and

an upper portion spaced apart from the lower conductor, and

the lower conductor and the lower portion of the upper conductor include a same metallic material.

3 . The semiconductor package as claimed in claim 2 , wherein the lower conductor and the lower portion of the upper conductor each include bismuth.

4 . The semiconductor package as claimed in claim 2 , wherein the upper portion of the upper conductor does not include bismuth.

5 . The semiconductor package as claimed in claim 1 , wherein the first surface of the dielectric pattern is curved.

6 . The semiconductor package as claimed in claim 5 , wherein the first surface conforms to a surface of the upper conductor.

7 . The semiconductor package as claimed in claim 5 , wherein the third surface is curved and conforms to the first surface.

8 . The semiconductor package as claimed in claim 1 , wherein the second surface of the dielectric pattern is flat.

9 . The semiconductor package as claimed in claim 1 , wherein a thickness of the dielectric pattern is equal to or greater than about 10 nm.

10 . A semiconductor package, comprising:

a connection structure including a lower conductor, an upper conductor connected to the lower conductor, and a dielectric pattern that at least partially surrounds the upper conductor;

a first structure including an upper connection pattern connected to the lower conductor and an upper dielectric layer that surrounds the lower conductor; and

a second structure including a lower connection pattern connected to the upper conductor and a lower dielectric layer that surrounds the upper conductor,

wherein the dielectric pattern is in contact with a bottom surface of the lower dielectric layer of the second structure, and

wherein the upper dielectric layer of the first structure is spaced apart from the lower connection pattern and the lower conductor.

11 . The semiconductor package as claimed in claim 10 , wherein:

the upper connection pattern of the first structure includes a sidewall exposed at an outside of the first structure, and

the lower conductor covers at least a part of the sidewall.

12 . The semiconductor package as claimed in claim 11 , wherein the lower conductor covers an upper portion of the sidewall.

13 . The semiconductor package as claimed in claim 11 , wherein the lower conductor covers an entirety of the sidewall.

14 . The semiconductor package as claimed in claim 10 , further comprising a molding layer that surrounds the connection structure,

wherein the dielectric pattern includes:

a first surface in contact with the upper conductor;

a second surface in contact with the lower conductor; and

a third surface in contact with the molding layer.

15 . The semiconductor package as claimed in claim 14 , wherein the first surface and the third surface of the dielectric pattern are curved.

16 . The semiconductor package as claimed in claim 15 , wherein the second surface of the dielectric pattern is flat.

17 . A semiconductor package, comprising:

a first structure including an upper connection pattern and an upper dielectric layer;

a second structure including a lower connection pattern and a lower dielectric layer that faces the upper dielectric layer of the first structure;

a connection structure that connects the upper connection pattern of the first structure to the lower connection pattern of the second structure; and

a molding layer that surrounds the connection structure and the second structure,

wherein:

the connection structure includes:

a lower conductor connected to the upper connection pattern of the first structure;

an upper conductor connected to the lower conductor and the lower connection pattern of the second structure; and

a dielectric pattern that at least partially surrounds the upper conductor and contacts a bottom surface of the lower dielectric layer,

the dielectric pattern includes:

a first surface in contact with the upper conductor;

a second surface in contact with the lower conductor; and

a third surface in contact with the molding layer,

the first surface and the third surface of the dielectric pattern are curved, and

the second surface is a lowermost surface of the dielectric pattern.

18 . The semiconductor package as claimed in claim 17 , wherein:

the upper conductor includes:

a lower portion in contact with the lower conductor; and

an upper portion spaced apart from the lower conductor, and

the lower portion of the upper conductor includes bismuth.

19 . The semiconductor package as claimed in claim 18 , wherein the upper portion of the upper conductor does not include bismuth.

20 . The semiconductor package as claimed in claim 17 , wherein the second surface is a flat surface in contact with a surface of the lower conductor facing the second structure.