IP Library › Granted Patent US 12677647
Granted Patent B2
US 12677647 · App. 17/451,686 · Granted Jul 7, 2026

Diffusion prevention spacer

Inventors: Chanro Park (Clifton Park, NY); Koichi Motoyama (Clifton Park, NY); Kenneth Chun Kuen Cheng (Shatin, HK); Chih-Chao Yang (Glenmont, NY)
Assignee: International Business Machines Corporation
H10W20/035H10W20/037H10W20/069H10W20/089H10W20/098H10W20/42H10W20/425H10W20/435
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Quick Facts
Patent No.
US 12677647
App. No.
17/451,686
Granted
Jul 7, 2026
Kind
B2
Abstract

A method of making a semiconductor component includes forming an interconnect in a dielectric layer such that an uppermost surface of the interconnect is substantially coplanar with an uppermost surface of the dielectric layer. The method further includes recessing the dielectric layer such that the uppermost surface of the dielectric layer is lower than the uppermost surface of the interconnect. The method further includes forming spacers in direct contact with the uppermost surface of the recessed dielectric layer such that the spacers are in direct contact with the interconnect. The method further includes recessing the interconnect such that the uppermost surface of the interconnect remains above the uppermost surface of the recessed dielectric layer and is lower than an uppermost surface of the spacers.

Claims (41)

1 . A semiconductor component, comprising:

a dielectric layer having an uppermost surface;

a further dielectric layer arranged above the uppermost surface of the dielectric layer;

an interconnect formed in the dielectric layer, wherein the interconnect is comprised of a plurality of interconnect elements, wherein each of the plurality of interconnect elements have a first tapered sidewall and an uppermost surface that is arranged higher than the uppermost surface of the dielectric layer;

a liner layer located around each of the plurality of interconnect elements;

a barrier layer located around the liner layer;

a further interconnect that includes a plurality of further interconnect elements, wherein each of the further interconnect elements have a second tapered sidewall, the further interconnect formed in the further dielectric layer such that the one of plurality of further interconnect elements is in direct contact with one of the plurality of the interconnect elements;

a metal line connecting two of the plurality of further interconnect elements, wherein the metal line extends over a bypassed interconnect element, wherein the bypassed interconnect element is located between two of the plurality of interconnect elements that are connected to two of the plurality of further interconnect elements;

a spacer comprising an uppermost surface that is arranged higher than the uppermost surface of the interconnect, a bottom surface in direct contact with the uppermost surface of the dielectric layer, a first internal side surface in direct contact with the first tapered sidewall of the interconnect, and a second internal side surface in direct contact with the second tapered sidewall of the further interconnect, wherein the spacer is in contact with the barrier layer located around each of the plurality of interconnect elements; and

a capping layer located on top of the bypassed interconnect element, wherein a bottom surface of the capping layer is in contact with a top surface of the bypassed interconnect element, a top surface of the liner layer, and a top surface of the barrier layer, wherein the capping layer is in contact with a side surface of the spacer, wherein the spacer extends past a top surface of the capping layer.

2 . The semiconductor component of claim 1 , wherein:

the first tapered sidewall extends above the uppermost surface of the dielectric layer.

3 . The semiconductor component of claim 1 , wherein:

the interconnect includes:

a barrier arranged in direct contact with the dielectric layer,

a liner arranged in direct contact with the barrier, and

an interconnect body arranged in direct contact with the liner.

4 . The semiconductor component of claim 1 , further comprising:

an etch stop layer between and in direct contact with the dielectric layer and the further dielectric layer.

5 . The semiconductor component of claim 4 , wherein:

the further interconnect is in direct contact with the interconnect at an interface, and

the interface is arranged higher than the uppermost surface of the dielectric layer and lower than the uppermost surface of the spacer.

6 . The semiconductor component of claim 4 , wherein:

the etch stop layer is in direct contact with and respectively between the further dielectric layer and the spacer.

7 . A semiconductor component, comprising:

a lower level dielectric having an uppermost surface;

a upper level dielectric arranged above the uppermost surface of the lower level dielectric;

a lower interconnect formed in the lower level dielectric, wherein the lower interconnect is comprised of a plurality of lower interconnect elements, wherein each of the plurality of lower interconnect elements have a first tapered sidewall and an uppermost surface that is arranged higher than the uppermost surface of the lower level dielectric;

a liner layer located around each of the plurality of interconnect elements;

a barrier layer located around the liner layer;

an upper interconnect that includes a plurality of further upper interconnect elements, wherein each of the upper interconnect elements have a second tapered sidewall, the upper interconnect formed in the upper level dielectric such that the one of plurality upper interconnect elements is in direct contact with one of the plurality of the lower interconnect elements;

a metal line connecting two of the plurality of upper interconnect elements, wherein the metal line extends over a bypassed lower interconnect element, wherein the bypassed interconnect is located between two of the plurality of lower interconnect elements that are connected to two of the plurality of upper interconnect elements;

a spacer comprising an uppermost surface that is arranged higher than the uppermost surface of the lower interconnect, a bottom surface in direct contact with the uppermost surface of the lower level dielectric, a first internal side surface in direct contact with the first tapered sidewall of the lower interconnect, and a second internal side surface in direct contact with the second tapered sidewall of the upper interconnect, wherein the spacer is in contact with the barrier layer located around each of the plurality of interconnect elements; and

a capping layer located on top of the bypassed interconnect element, wherein a bottom surface of the capping layer is in contact with a top surface of the bypassed interconnect element, a top surface of the liner layer, and a top surface of the barrier layer, wherein the capping layer is in contact with a side surface of the spacer, wherein the spacer extends past a top surface of the capping layer.

8 . The semiconductor component of claim 7 , wherein:

the first tapered sidewall of the lower interconnect extend partially above the uppermost surface of the lower level dielectric.

9 . The semiconductor component of claim 7 , wherein:

the upper interconnect is in direct contact with the lower interconnect at an interface, and

the interface is arranged higher than the uppermost surface of the lower level dielectric and lower than the uppermost surface of the spacers.

10 . The semiconductor component of claim 7 , wherein:

the upper interconnect is in direct contact with the spacer.