Semiconductor memory device
According to one embodiment, a semiconductor memory device incudes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one; and a contact that extends in the stacked body in the stacking direction, and is connected to a structure arranged on in the stacked body or below the stacked body. The contact includes: a second conductive layer that extends in the stacked body LM in the stacking direction, and serves as a core of the contact; and a second insulating layer that covers a sidewall of the second conductive layer, and serves as a liner of the contact. At least at a point close to the structure, when viewed in a cross section taken in a direction intersecting the stacking direction, a variation, in a circumferential direction of the contact, of a first distance from a center point of the second conductive layer to an outer edge of the second insulating layer is larger than a variation, in the circumferential direction of the contact, of a second distance from the center point to an outer edge of the second conductive layer.
1 . A semiconductor memory device comprising:
a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one;
a plurality of pillars that extends in the stacked body in a stacking direction of the stacked body, and each forms a memory cell at respective intersections with at least a part of the plurality of first conductive layers; and
a contact that extends in the stacked body in the stacking direction, and is connected to a structure arranged in the stacked body or below the stacked body,
the contact comprising:
a second conductive layer that extends in the stacked body in the stacking direction, and serves as a core of the contact; and
a second insulating layer that covers a sidewall of the second conductive layer, and serves as a liner of the contact, and
a first variation being larger than a second variation,
wherein
the first variation and the second variation are on a cross section of the contact intersecting the stacking direction including a portion of the contact close to the structure in the stacking direction,
the first variation is a variation among first distances from a center point of the second conductive layer to any points on an outer edge of the second insulating layer,
the second variation is a variation among second distances from the center point of the second conductive layer to any points on an outer edge of the second conductive layer, and
the first variation on the cross section including the portion of the contact is larger than a third variation among the first distances on another cross section of the contact intersecting the stacking direction including another portion of the contact farther away from the structure in the stacking direction than the portion of the contact is.
2 . The semiconductor memory device according to claim 1 , wherein
the second insulating layer includes, at least at the portion of the contact,
a third insulating layer that is arranged on an outer circumferential side of the contact while including the outer edge of the second insulating layer; and
a fourth insulating layer that is arranged to adjoin the outer edge of the second conductive layer, and on an inner side of the contact than the third insulating layer.
3 . The semiconductor memory device according to claim 2 , wherein
the third insulating layer continuously covers a circumference of the second conductive layer, and
the fourth insulating layer continuously or intermittently covers the circumference of the second conductive layer.
4 . The semiconductor memory device according to claim 2 , wherein
the fourth insulating layer is not arranged at another portion of the contact farther away from the structure in the stacking direction than the portion of the contact is.
5 . The semiconductor memory device according to claim 2 , wherein
an average grain diameter of crystals contained in the fourth insulating layer is larger than an average grain diameter of crystals contained in the third insulating layer.
6 . The semiconductor memory device according to claim 2 , wherein
the third insulating layer contains silicon oxide, and
the fourth insulating layer contains silicon oxynitride.
7 . The semiconductor memory device according to claim 2 , wherein
an end portion of the fourth insulating layer close to the structure in the stacking direction terminates below an end portion of the third insulating layer close to the structure in the stacking direction.
8 . The semiconductor memory device according to claim 2 , wherein
an end portion of the fourth insulating layer close to the structure in the stacking direction is arranged on the outer circumferential side of the contact, than an end portion of the third insulating layer close to the structure in the stacking direction.
9 . The semiconductor memory device according to claim 2 , wherein
an end portion of the third insulating layer close to the structure in the stacking direction is arranged on the outer circumferential side of the contact, than an end portion of the fourth insulating layer close to the structure in the stacking direction.
10 . A semiconductor memory device comprising:
a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one;
a plurality of pillars that extends in the stacked body in a stacking direction of the stacked body, and each forms a memory cell at respective intersections with at least a part of the plurality of first conductive layers; and
a contact that extends in the stacked body in the stacking direction, and is connected to a structure arranged in the stacked body or below the stacked body,
the contact comprising:
a second conductive layer that extends in the stacked body in the stacking direction, and serves as a core of the contact; and
a second insulating layer that covers a sidewall of the second conductive layer, and serves as a liner of the contact, and
at least at a portion of the contact close to the structure in the stacking direction, a roughness of an outer circumferential face of the second conductive layer, is lower than a roughness of an outer circumferential face of the second insulating layer.
11 . The semiconductor memory device according to claim 10 , wherein
the roughness of the second insulating layer at the portion of the contact is higher than the roughness of the second insulating layer at another portion of the contact farther away from the structure in the stacking direction than the portion of the contact is.
12 . The semiconductor memory device according to claim 10 , wherein
the second insulating layer includes, at least at the portion of the contact,
a third insulating layer that is arranged on an outer circumferential side of the contact while including the outer circumferential face of the second insulating layer; and
a fourth insulating layer that is arranged to adjoin the outer circumferential face of the second conductive layer, and on an inner side of the contact than the third insulating layer.
13 . The semiconductor memory device according to claim 12 , wherein
the third insulating layer continuously covers a circumference of the second conductive layer, and
the fourth insulating layer continuously or intermittently covers the circumference of the second conductive layer.
14 . The semiconductor memory device according to claim 12 , wherein
the fourth insulating layer is not arranged at another portion of the contact farther away from the structure in the stacking direction than the portion of the contact is.
15 . The semiconductor memory device according to claim 12 , wherein
an average grain diameter of crystals contained in the fourth insulating layer is larger than an average grain diameter of crystals contained in the third insulating layer.
16 . The semiconductor memory device according to claim 12 , wherein
the third insulating layer contains silicon oxide, and
the fourth insulating layer contains silicon oxynitride.
17 . A semiconductor memory device comprising:
a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one;
a plurality of pillars that extends in the stacked body in a stacking direction of the stacked body, and each forms a memory cell at respective intersections with at least a part of the plurality of first conductive layers; and
a contact that extends in the stacked body in the stacking direction, and is connected to one of the plurality of first conductive layers,
the contact comprising:
a second conductive layer that extends in the stacked body in the stacking direction, and serves as a core of the contact; and
a second insulating layer that covers a sidewall of the second conductive layer, and serves as a liner of the contact,
a first variation being larger than a second variation,
wherein
the first variation and the second variation are on a cross section of the contact intersecting the stacking direction including a portion of the contact close to the one of the plurality of first conductive layers in the stacking direction,
the first variation is a variation among first distances from a center point of the second conductive layer to any points on an outer edge of the second insulating layer,
the second variation is a variation among second distances from the center point of the second conductive layer to any points on an outer edge of the second conductive layer, and
the first variation on the cross section including the portion of the contact is larger than a third variation among the first distances on another cross section of the contact intersecting the stacking direction and including another portion of the contact farther away from the one of the plurality of first conductive layers in the stacking direction than the portion of the contact is.
18 . The semiconductor memory device according to claim 17 , wherein
the second insulating layer includes, at least at the portion of the contact,
a third insulating layer that is arranged on an outer circumferential side of the contact while including the outer edge of the second insulating layer; and
a fourth insulating layer that is arranged to adjoin the outer edge of the second conductive layer, and on an inner side of the contact than the third insulating layer.