Semiconductor structures and method for manufacturing a semiconductor structure
A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first redistribution layer (RDL), a second RDL, and a contact feature. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via, wherein the active area is disposed between the trench capacitor and the first RDL. The second RDL is disposed over the back surface and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the first RDL and electrically connecting to the trench capacitor through the first RDL, the through via and the second RDL. A method of manufacturing the semiconductor structure is also provided.
1 . A semiconductor structure comprising:
a substrate, having a front surface, a back surface opposite to the front surface, and an active area at a front surface;
a through via, penetrating the substrate and having a top surface at the front surface of the substrate and a bottom surface at the back surface of the substrate;
a trench capacitor, extending from a back surface toward the front surface, wherein the trench capacitor is separated from the active area;
a first redistribution layer (RDL), disposed over the front surface of the substrate, and electrically connecting to the through via, wherein the active area is disposed between the trench capacitor and the first RDL;
a second RDL, disposed over the back surface of the substrate, and electrically connecting to the through via and the trench capacitor; and
a contact feature, disposed over the first RDL and electrically connecting to the trench capacitor through the first RDL, the through via and the second RDL.
2 . The semiconductor structure of claim 1 , wherein a depth of the trench capacitor is substantially less than a depth of the through via measured from the back surface of the substrate.
3 . The semiconductor structure of claim 1 , wherein the through via comprises a via dielectric layer and a via metal surrounded by the via dielectric layer.
4 . The semiconductor structure of claim 3 , wherein the via metal is electrically isolated from the active area by the via dielectric layer.
5 . The semiconductor structure of claim 1 , further comprising:
a bonding layer, disposed over the second RDL and comprising a dielectric material.
6 . The semiconductor structure of claim 5 , wherein the bonding layer further comprises a metallic material surrounded by the dielectric material and disposed at a surface of the bonding layer opposite to the second RDL.
7 . The semiconductor structure of claim 1 , wherein the second RDL comprises different conductive vias, and the trench capacitor includes a first electrode and a second electrode electrically connecting to the different conductive vias of the second RDL.
8 . The semiconductor structure of claim 1 , wherein
the contact feature is a first contact feature of a plurality of contact features,
the second RDL and the plurality of contact features are in a first chip, and
the semiconductor structure further comprises:
a second chip, disposed over the second RDL and bonded to the first chip through a hybrid bonding layer.
9 . The semiconductor structure of claim 8 , further comprising:
a support substrate, disposed over the first RDL and electrically connecting the first chip through the plurality of contact features.
10 . The semiconductor structure of claim 9 , further comprising:
an interposer, disposed over the first RDL and bonded to the first chip through the plurality of contact features, wherein the support substrate electrically connects to the first chip through the interposer.
11 . The semiconductor structure of claim 8 , wherein the first chip is a memory chip, and the second chip is a logic chip.
12 . The semiconductor structure of claim 8 , wherein a distance between an active region of the second chip and the trench capacitor is less than 30 microns.
13 . The semiconductor structure of claim 1 , wherein the second RDL includes a plurality of metal line layers, and a number of the metal line layers is less than 5.
14 . A semiconductor structure comprising:
a substrate, having a front surface, a back surface opposite to the front surface, and an active area at a front surface;
a through via, penetrating the substrate;
a trench capacitor, extending from a back surface toward the front surface, wherein the trench capacitor is separated from the active area;
a second redistribution layer (RDL), disposed over the back surface of the substrate, and electrically connecting to the through via and the trench capacitor; and
a first chip disposed over the second RDL, comprising a first bonding layer disposed over a front surface of the first chip, wherein the front surface of the first chip faces the back surface of the substrate.
15 . The semiconductor structure of claim 14 , further comprising a second bonding layer between the second RDL and the first bonding layer.
16 . The semiconductor structure of claim 14 , further comprising a first RDL disposed over the front surface of the substrate, and electrically connecting to the through via.
17 . The semiconductor structure of claim 16 , further comprising a support substrate electrically connecting to the first RDL through a plurality of contact features.
18 . The semiconductor structure of claim 16 , further comprising an interposer between the first RDL and the support substrate, wherein the interposer is electrically connected to the first RDL and the support substrate.
19 . The semiconductor structure of claim 14 , the trench capacitor further comprises:
a first electrode configured to receive a first voltage; and
a second electrode configured to receive a second voltage.
20 . The semiconductor structure of claim 14 , further comprising a dielectric layer disposed over the second RDL and surrounding the first chip.