Self-aligned buried power rail formation for semiconductor devices
A self-aligned buried power rail having an adjustable height is formed between a first semiconductor device region and a second semiconductor device region. The self-aligned buried power rail having the adjustable height has improved conductivity. Notably, the self-aligned buried power rail has a first portion having a first height that is present in a gate cut trench and a second portion having a second height, which is greater than the first height, that is present in a source/drain cut trench.
1 . A semiconductor structure comprising:
a first semiconductor device region comprising at least one semiconductor device;
a second semiconductor device region comprising at least one other semiconductor device;
a buried power rail located between the first semiconductor device region and the second semiconductor device region, wherein a first portion of the buried power rail having a first height is present in a gate cut trench and terminates on a first surface of a shallow trench isolation structure, a second portion of the buried power rail having a second height, which is greater than the first height, is present in a source/drain cut trench and terminates on a second surface of the shallow trench isolation structure, and a third portion of the buried power rail that is located between a source/drain region of the at least one semiconductor device and a source/drain region of the at least on other semiconductor device is entirely surrounded by, and entirely embedded in, the shallow trench isolation structure; and
a conductive contact structure directly contacting at least the source/drain region of the at one semiconductor device present in the first semiconductor device region and the second portion of the buried power rail that is present in the source/drain cut trench.
2 . The semiconductor structure of claim 1 , wherein the conductive contact structure further directly contacts the source/drain region of the at least one other semiconductor device that is present in the second semiconductor device region.
3 . The semiconductor structure of claim 1 , further comprising another conductive contact structure directly contacting the source/drain region of the at least one other semiconductor device that is present in the second semiconductor device region.
4 . The semiconductor structure of claim 1 , wherein the first portion of the buried power rail and the second portion of the buried power rail are composed of a single electrically conductive power rail material.
5 . The semiconductor structure of claim 1 , wherein the second portion of the buried power rail is composed of a buried power rail conductive material layer and an additional buried power rail conductive material, and the first portion of the buried power rail is composed of only the buried power rail conductive material layer.
6 . The semiconductor structure of claim 5 , wherein the buried power rail conductive material layer and an additional buried power rail conductive material are composed of a compositionally different electrically conductive power rail material.
7 . The semiconductor structure of claim 1 , wherein the first portion of the buried power rail is located entirely beneath a topmost surface of the shallow trench isolation structure and the second portion of the buried power rail has an upper portion that extends above the topmost surface of the shallow trench isolation structure.
8 . The semiconductor structure of claim 1 , wherein the at least one semiconductor device present in the first semiconductor device region comprises a nanosheet containing device, a finFET containing semiconductor device, a semiconductor nanowire containing device or at least one planar semiconductor device, and the at least one other semiconductor device present in the second semiconductor device region comprises a nanosheet containing device, a finFET containing semiconductor device, a semiconductor nanowire semiconductor device, or a planar semiconductor device.
9 . The semiconductor structure of claim 8 , wherein the at least one semiconductor device present in the first semiconductor device region comprises a first combined sheet device, and the at least one other semiconductor device present in the second semiconductor device region comprises a second combined sheet device, wherein the first combined sheet device comprises a first nanosheet device and a second nanosheet device, wherein the first nanosheet device is located on a first side of a first dielectric pillar and the second nanosheet device is located on a second side of the first dielectric pillar, and the first side of the first dielectric pillar is opposite the second side of the first dielectric pillar; and the second combined sheet device comprises a third nanosheet device and a fourth nanosheet device, wherein the third nanosheet device is located on a first side of a second dielectric pillar and the fourth nanosheet device is located on a second side of the second dielectric pillar, and the first side of the second dielectric pillar is opposite the second side of the second dielectric pillar, and wherein the second nanosheet device of the first combined sheet device faces the third nanosheet device of the second combined sheet device.