Interconnection structure, semiconductor device with interconnection structure and method for fabricating the same
Various embodiments of the present disclosure improve integration degree of semiconductor devices by simultaneously forming interconnections extending in various directions through a single gap-fill process. The embodiments of the present invention provide an interconnection structure that is capable of simplifying semiconductor processing, a semiconductor device including the interconnection structure, and a method for fabricating the semiconductor device. According to an embodiment of the present disclosure, an interconnection structure comprises: a stack of a plurality of interconnections, wherein at least two layers of the plurality of interconnections extend in different directions, and a portion of a top surface of a lower interconnection of the at least two layers is in direct contact with a portion of a bottom surface of an upper interconnection of the at least two layers.
1 . A semiconductor device comprising:
a first interconnection extending in a first direction over a substrate;
a first contact connecting the first interconnection and the substrate;
a second interconnection formed over the first interconnection, in direct contact with a portion of the first interconnection and extending in a second direction which is different from the first direction;
a third interconnection formed over the second interconnection and extending in a third direction which is different from the first and second directions; and
a second contact of which both ends are in direct contact with the second interconnection and the third interconnection,
wherein the first contact is vertically aligned with the second contact,
wherein a top surface of the first interconnection and a bottom surface of the second interconnection are located at a same level,
wherein the sidewalls of the first and second contacts are vertically aligned in a cross-sectional view, and
wherein the vertical alignment of the sidewalls of the first and second contacts reduces parasitic capacitance and improves signal integrity.
2 . The semiconductor device of claim 1 , wherein a line width of the second interconnection is the same as a line width of the first interconnection or greater than the line width of the first interconnection.
3 . The semiconductor device of claim 1 , wherein the third interconnection is formed in direct contact with a portion of the second interconnection.
4 . The semiconductor device of claim 3 , wherein a top surface of the second interconnection and a bottom surface of the third interconnection are located at a same level.
5 . The semiconductor device of claim 3 , wherein a line width of the third interconnection is the same as a line width of the second interconnection or greater than the line width of the second interconnection.
6 . The semiconductor device of claim 1 , wherein a top surface of the second interconnection is located at a lower level than a bottom surface of the third interconnection.
7 . A semiconductor device comprising:
a first interconnection formed over a substrate and extending in a first direction;
a first contact connecting the first interconnection and the substrate;
a second interconnection formed over the first interconnection and extending in a second direction;
a second contact connecting the first and second interconnections; and
a third interconnection formed over the second interconnection, in direct contact with a portion of the second interconnection, and extending in a third direction which is different from the first and second directions,
wherein the first contact is vertically aligned with the second contact,
wherein a top surface of the first interconnection and a bottom surface of the second interconnection are located at a same level,
wherein the sidewalls of the first and second contacts are vertically aligned in a cross-sectional view, and
wherein the vertical alignment of the first and second contacts reduces parasitic capacitance and improves signal integrity.
8 . The semiconductor device of claim 7 , wherein a line width of the third interconnection is the same as a line width of the second interconnection or greater than the line width of the second interconnection.
9 . The semiconductor device of claim 7 , wherein thicknesses of the second and third interconnections are smaller than a thickness of the first interconnection.
10 . The semiconductor device of claim 7 , further including a fourth interconnection formed over the third interconnection, in direct contact with a portion of the third interconnection, and extending in a fourth direction which is different from the third direction.
11 . The semiconductor device of claim 10 , wherein a top surface of the third interconnection and a bottom surface of the fourth interconnection are located at a same level.
12 . The semiconductor device of claim 10 , wherein a line width of the fourth interconnection is the same as a line width of the third interconnection or greater than the line width of the third interconnection.
13 . The semiconductor device of claim 10 , wherein a line width of the fourth interconnection is smaller than a line width of the first interconnection.
14 . The semiconductor device of claim 7 , further including:
a fourth interconnection formed over the third interconnection and extending in a fourth direction; and
a third contact of which both ends are in direct contact with the third and fourth interconnections.