Semiconductor device and manufacturing method thereof
View Patent ↗A fabrication method is disclosed. The fabrication method includes: forming, on a substrate, a transistor comprising a source, drain, and gate; forming a multi-layer interconnection structure configured to provide electrical connections for the source, drain, and gate, wherein the multi-layer interconnection structure has a plurality of interconnection layers; forming a metal-insulator-metal (MiM) capacitor in the interconnection structure, the MiM capacitor comprising a first electrode, a high-K spacer with a first vertically-extending sidewall and a second vertically-extending sidewall wherein the first vertically-extending sidewall has a vertically extending interface with the first electrode, and a second electrode wherein the second vertically-extending sidewall has a vertically extending interface with the second electrode; forming a first conductive feature that connects to the first electrode; and forming a second conductive feature that connects to the second electrode.
1 . A method, comprising:
forming, on a substrate, a transistor comprising a source, drain, and gate;
forming a multi-layer interconnection structure configured to provide electrical connections for the source, drain, and gate, wherein the multi-layer interconnection structure has a plurality of interconnection layers; and
forming a metal-insulator-metal (MiM) capacitor in the interconnection structure, the MiM capacitor comprising a first electrode, a second electrode, and a high-K spacer having a first vertically-extending sidewall and a second vertically-extending sidewall disposed between the first electrode and the second electrode, wherein:
the first electrode, the second electrode, and the high-K spacer extend from a top surface of a first intermetal dielectric (IMD) layer to a bottom surface of the first IMD layer; and
the first vertically-extending sidewall has a vertically extending interface with the first electrode, and the second vertically-extending sidewall has a vertically extending interface with the second electrode.
2 . The method of claim 1 , further comprising:
forming a first conductive feature that connects to the first electrode; and
forming a second conductive feature that connects to the second electrode;
wherein forming the first conductive feature and forming the second conductive feature comprises forming the first conductive feature and the second conductive features in different interconnection layers in the interconnection structure.
3 . The method of claim 1 , further comprising:
forming a first conductive feature that connects to the first electrode; and
forming a second conductive feature that connects to the second electrode;
wherein forming the first conductive feature and forming the second conductive feature comprises forming the first conductive feature and the second conductive features in a same interconnection layer of the interconnection structure.
4 . The method of claim 1 , wherein forming the MiM capacitor comprises forming the first electrode, the high-K spacer, and the second electrode in a same interconnection layer of the interconnection structure.
5 . The method of claim 1 , wherein forming the MiM capacitor comprises:
patterning a first IMD layer of the multi-layer interconnection structure to define a patterned section of the first IMD layer surrounded by an opening in the first IMD layer;
forming the high-K spacer in the opening on sidewalls of the first IMD layer that face the opening;
removing inner portions of the patterned section while leaving the high-K spacer;
forming a barrier-seed layer on the high-K spacer and exposed portions of a second IMD layer below the first IMD layer; and
forming the first electrode and the second electrode in the first IMD layer over the exposed portions of the second IMD layer.
6 . The method of claim 5 , wherein the second electrode has a similar shape to the patterned section of the first IMD layer.
7 . A semiconductor device, comprising:
a transistor comprising a source, drain, and gate on a substrate;
a multi-layer interconnection structure, on the substrate, configured to provide electrical connections for the source, drain, and gate, wherein the multi-layer interconnection structure has a plurality of interconnection layers;
a metal-insulator-metal (MiM) capacitor, in the interconnection structure, comprising a first electrode, a high-K spacer, and a second electrode all extending from a top surface of a first intermetal dielectric (IMD) layer to a bottom surface of the first IMD layer;
a first conductive feature that connects to the first electrode; and
a second conductive feature that connects to the second electrode.
8 . The semiconductor device of claim 7 , wherein the high-K spacer has a first vertically-extending sidewall that has a vertically extending interface with the first electrode, and a second vertically-extending sidewall that has a vertically extending interface with the second electrode.
9 . The semiconductor device of claim 7 , wherein the first conductive feature and the second conductive feature are formed in different interconnection layers in the interconnection structure.
10 . The semiconductor device of claim 7 , wherein the first conductive feature and the second conductive feature are formed in a same interconnection layer of the interconnection structure.
11 . The semiconductor device of claim 7 , wherein the second electrode has a single comb-like shape with a body section and a plurality of teeth sections extending out on one side of the body section in parallel from the body section.
12 . The semiconductor device of claim 7 , wherein the second electrode has a double comb-like shape with a body section and a plurality of teeth sections extending out on two sides of the body section in parallel from the body section.
13 . The semiconductor device of claim 7 , wherein the second electrode has a spiral-like shape.
14 . A method, comprising:
providing a substrate with a multi-layer interconnection structure having a first IMD layer and a second IMD layer;
patterning the first IMD layer of the multi-layer interconnection structure to define a patterned section of the first IMD layer surrounded by an opening in the first IMD layer;
forming a high-K spacer in the opening on sidewalls of the first IMD layer that face the opening;
removing inner portions of the patterned section while leaving the high-K spacer;
forming a barrier-seed layer on the high-K spacer and exposed portions of the second IMD layer below the first IMD layer; and
forming a first electrode and a second electrode in the first IMD layer over the exposed portions of the second IMD layer.
15 . The method of claim 14 , further comprising: forming a first conductive feature that connects to the first electrode; and forming a second conductive feature that connects to the second electrode, wherein the first conductive feature and the second conductive feature are formed in different layers in the interconnection structure.
16 . The method of claim 14 , further comprising: forming a first conductive feature that connects to the first electrode; and forming a second conductive feature that connects to the second electrode, wherein the first conductive feature and the second conductive feature are formed in a same layer in the interconnection structure.
17 . The method of claim 14 , wherein the second electrode has a shape similar to the patterned section of the first IMD layer.
18 . The method of claim 14 , wherein the second electrode has a single comb-like shape with a body section and a plurality of teeth sections extending out on one side of the body section in parallel from the body section.
19 . The method of claim 14 , wherein the second electrode has a double comb-like shape with a body section and a plurality of teeth sections extending out on two sides of the body section in parallel from the body section.
20 . The method of claim 14 , wherein the second electrode has a spiral-like shape.