Package with thermal conductive material interspersed in depopulated regions of solder bumps
The present disclosure relates to radio frequency (RF) chip packages and, more particularly, to improved thermal performance of RF chip packages and methods of manufacture. The structure includes: a board; a chip substrate; a pattern of solder bumps between the board and the chip substrate; and a thermal conductive material between the chip substrate and the board in depopulated regions of solder bumps of the chip substrate.
1 . A structure comprising:
a board;
a chip substrate;
a pattern of solder bumps between the board and the chip substrate;
a thermal conductive material between the chip substrate and the board in depopulated regions of solder bumps of the chip substrate; and
underfill material provided between the chip substrate and the board and interspersed within the pattern of solder bumps, wherein the board is a redistribution layer connected to both the chip substrate and a second board, and the thermal conductive material is in contact with the redistribution layer and the second board.
2 . The structure of claim 1 , wherein the pattern of solder bumps comprise a ball grid array.
3 . The structure of claim 1 , wherein the thermal conductive material is in physical contact with the chip substrate and the board and the underfill material.
4 . The structure of claim 3 , wherein the depopulated regions are regions of the chip substrate that are devoid of the solder bumps in an interior portion or edges of the chip.
5 . The structure of claim 4 , wherein the underfill material is interspersed within and makes contact with the solder bumps and is at edges between the chip substrate and the board.
6 . The structure of claim 5 , wherein the underfill material and the thermal conductive material are different materials which contact in the depopulated regions.
7 . The structure of claim 1 , wherein the thermal conductive material is a die cut thermal interface material.
8 . The structure of claim 1 , further comprising a laminate structure between the chip substrate and the board, wherein the thermal conductive material is in contact with the laminate structure and the chip substrate.
9 . The structure of claim 8 , wherein the thermal conductive material is in an area devoid of pins that connect the laminate structure to the chip substrate.
10 . The structure of claim 1 , wherein the thermal conductive material is a region between the redistribution layer and the board that is devoid of solder bumps that bond the redistribution layer to the board.
11 . A structure comprising:
a first board;
a second board;
a ball grid array connecting the first board to the second board;
a thermal conductive material between the first board and the second board in regions which are devoid of the ball grid array;
underfill material provided between the first board and the second board and interspersed within the ball grid array and contacting the thermal conductive material in the regions which are devoid of the ball grid array; and
a chip substrate, wherein the first board is a redistribution layer connected to both the chip substrate and the second board, and the thermal conductive material is in contact with the redistribution layer and the second board.
12 . The structure of claim 11 , wherein the second board is a chip substrate, the ball grid array bonds the chip substrate to the first board, and the thermal conductive material is a thermal interface material.
13 . The structure of claim 12 , wherein the thermal conductive material is in physical contact with the chip substrate and the first board.
14 . The structure of claim 13 , wherein the underfill material extends to outer edges thereof between the first board and the second board.
15 . The structure of claim 14 , wherein the underfill material and the thermal conductive material have different thermal conductivity properties and viscosities.
16 . The structure of claim 11 , wherein the thermal conductive material is a die cut thermal interface material.
17 . A method comprising:
placing thermal conductive material in regions of one of a chip substrate and a board that is devoid of solder bumps;
placing underfill material between a first board and a second board and interspersed within the solder bumps and contacting the thermal conductive material in the regions which are devoid of solder bumps; and
connecting the chip substrate to the board by applying a force such that the thermal conductive material is squeezed and in physical contact with both the chip substrate and the board,
wherein the first board is a redistribution layer connected to both the chip substrate and the second board, and the thermal conductive material is in contact with the redistribution layer and the second board.