Substrates for power stage assemblies comprising bottom-cooled semiconductor power switching devices
A multi-zone substrate for a power stage assembly comprising at least one bottom-cooled semiconductor power switching device and driver components, for integration on a common substrate. A first zone provides electrical connections and a thermal pad for mounting at least one bottom-cooled semiconductor switching device, the first zone comprising dielectric and conductive layers which provide a power substrate optimized for thermal performance. A second zone provides electrical connections for mounting driver components, the second zone comprising dielectric and conductive layers providing a driver substrate optimized for electrical performance. For example, the first zone comprises a single layer metal interconnect structure with a first thermal resistance, the second zone comprises a multi-layer metal interconnect structure with a second thermal resistance, the first thermal resistance being less than the second thermal resistance. The power stage assembly may comprise a multi-zone substrate configured for a single switch, half-bridge or full-bridge switch topology.
1 . A substrate for a power stage assembly comprising at least one bottom-cooled semiconductor power switching device and driver components, comprising:
a first zone comprising electrical connections and a thermal pad for mounting the at least one bottom-cooled semiconductor switching device, the first zone comprising a layer structure optimized for thermal performance; and
a second zone comprising electrical connections for mounting driver components, the second zone comprising a layer structure optimized for electrical performance,
wherein the first zone has a first thermal resistance between the thermal pad and a bottom surface of the substrate, and the second zone has a second thermal resistance between top and bottom surfaces of the substrate, wherein the first thermal resistance is significantly less than the second thermal resistance.
2 . The substrate of claim 1 , wherein first zone has a first thermal resistance between the thermal pad and a bottom surface of the substrate, and the second zone has a second thermal resistance between top and bottom surfaces of the substrate, wherein the first thermal resistance is significantly less than the second thermal resistance.
3 . The substrate of claim 1 , wherein the first zone comprises one or more electrically conductive layers and the second zone comprises at least one additional electrically conductive layer.
4 . The substrate of claim 3 , wherein the first zone comprises a single electrically conductive layer and the second zone comprises a plurality of electrically conductive layers.
5 . The substrate of claim 3 , wherein the layer structures of the first and second zones comprise a dielectric core, a top conductive layer and a bottom conductive layer, and wherein the dielectric core of the first zone comprises an inlay of a material having a lower thermal resistance than the dielectric core of the second zone.
6 . The substrate of claim 5 , wherein the second zone comprises at least one intermediate conductive layer between the top conductive layer and the bottom conductive layer.
7 . The substrate of claim 5 , wherein the second zone comprises a plurality of intermediate conductive layers and dielectric layers between the top conductive layer and the bottom conductive layer.
8 . The substrate of claim 3 , wherein the conductive layers of the first zone are configured for a semiconductor power switching device comprising a half-bridge switch topology, each high-side switch and low-side switch of the half-bridge comprising one transistor switch or a plurality of transistor switches connected in parallel; and conductive layers of the second zone are configured for driver components for the high-side and the low-side switches.
9 . The substrate of claim 3 , wherein the conductive layers of the first zone are configured for a semiconductor power switching device comprising a full-bridge switch topology, each high-side switch and low-side switch of the full-bridge comprising one transistor switch or a plurality of transistor switches connected in parallel; and conductive layers of the second zone are configured for driver components for the high-side and the low-side switches.
10 . The substrate of claim 3 , wherein the conductive layers of the first zone are configured for a semiconductor power switching device comprising a single switch topology comprising one transistor switch or a plurality of transistor switches connected in parallel; and conductive layers of the second zone are configured for driver components of the single switch.
11 . An insulated metal substrate (IMS) for a power stage assembly comprising at least one bottom-cooled semiconductor power switching device and driver components comprising:
a metal support substrate;
a first zone comprising a single-metal IMS or a double-metal IMS structure comprising one or two conductive metal layers and a second zone comprising a multi-metal IMS structure comprising at least one additional conductive metal layer;
the first zone comprising electrical connections and a thermal pad for mounting the at least one bottom-cooled semiconductor switching device, a layer structure of the first zone being optimized for thermal performance; and
the second zone comprising electrical connections for mounting driver components, a layer structure of the second zone being optimized for electrical performance,
wherein the first zone has a first thermal resistance between the thermal pad and a bottom surface of the substrate, and the second zone has a second thermal resistance between top and bottom surfaces of the substrate, wherein the first thermal resistance is significantly less than the second thermal resistance.
12 . The insulated metal substrate (IMS) of claim 11 , wherein the first zone is a single-metal IMS structure and the second zone is a 2-metal IMS structure.
13 . The insulated metal substrate (IMS) of claim 11 , wherein the first zone is a single-metal IMS structure and the second zone is a multi-metal IMS structure.
14 . A substrate for a power stage assembly comprising at least one bottom-cooled semiconductor power switching device and driver components comprising:
a layer stack comprising
a first electrically conductive layer:
a dielectric core;
a second electrically conductive layer;
in a first zone, the second electrically conductive layer providing electrical connections and a thermal pad for mounting the at least one bottom-cooled semiconductor switching device, and a thermally conductive inlay extending through the dielectric core between the thermal pad of the second electrically conductive layer and the first electrically conductive layer; and
in a second zone, the first and second electrically conductive layers providing electrical connections for mounting driver components, the second zone comprising a layer structure optimized for electrical performance,
wherein the first zone has a first thermal resistance between the thermal pad and a bottom surface of the substrate, and the second zone has a second thermal resistance between top and bottom surfaces of the substrate, wherein the first thermal resistance is significantly less than the second thermal resistance.
15 . The substrate of claim 14 , wherein the second zone comprises at least one intermediate electrically conductive layer.
16 . The substrate of claim 15 , wherein the second zone comprises a plurality of intermediate electrically conductive layers.
17 . The substrate of claim 14 , wherein the thermally conductive inlay is a thermally conductive ceramic inlay.
18 . The substrate of claim 14 , wherein a separate thermally conductive inlay is provided for each power switching device.
19 . The substrate of claim 14 , wherein each thermally conductive inlay is shared by a plurality of power switching devices.
20 . The substrate of claim 14 , wherein the electrically conductive layers and dielectric layers are provided by an N-metal layer PCB structure, wherein for zone 2 , N is >2.
21 . A direct bond copper (DBC) type substrate for a power stage assembly comprising at least one bottom-cooled semiconductor power switching device and driver components comprising:
a support substrate comprising a thermally conductive ceramic material, a first electrically conductive metal layer on a bottom surface of the support substrate and a second electrically conductive metal layer on a top surface of the support substrate;
a second dielectric layer formed on the second electrically conductive layer and a third electrically conductive metal layer formed on the second dielectric layer;
a first zone comprising a single metal interconnect structure and a second zone comprising a multi-layer metal interconnect structure; the first zone comprising electrical connections and a thermal pad for mounting the at least one bottom-cooled semiconductor switching device, the first zone comprising layers optimized for thermal performance; and
a second zone comprising electrical connections for mounting driver components, the second zone comprising layers optimized for electrical performance,
wherein the first zone has a first thermal resistance between the thermal pad and a bottom surface of the substrate, and the second zone has a second thermal resistance between top and bottom surfaces of the substrate, wherein the first thermal resistance is significantly less than the second thermal resistance.
22 . The direct bond copper (DBC) type substrate of claim 21 , wherein the second zone comprises a plurality of additional dielectric layers and electrically conductive metal layers.
23 . A power stage assembly, comprising a substrate as defined in claim 1 , and at least one power semiconductor switching device and driver circuitry, configured for any one of;
a single switch topology;
a half-bridge switch topology;
a full-bridge switch topology.
24 . The power stage assembly of claim 23 , wherein each power switching device is provided as an embedded die package, wherein a thermal pad, and source, drain and gate contact pads are provided on a bottom side of the embedded die package.
25 . The power stage assembly of claim 24 , wherein each power switching device is a GaN HEMTs.
26 . The power stage assembly of claim 23 , wherein the substrate is mounted on a heatsink.
27 . A power stage assembly comprising:
a substrate;
at least one bottom-cooled semiconductor power switching device, and
driver components;
wherein the substrate comprises:
a first zone comprising electrical connections and a thermal pad for mounting the at least one bottom-cooled semiconductor switching device, the first zone comprising a layer structure optimized for thermal performance; and
a second zone comprising electrical connections for the mounting driver components, the second zone comprising a layer structure optimized for electrical performance,
wherein the first zone has a first thermal resistance between the thermal pad and a bottom surface of the substrate, and the second zone has a second thermal resistance between top and bottom surfaces of the substrate, wherein the first thermal resistance is significantly less than the second thermal resistance.
28 . The power stage assembly of claim 27 , wherein the first zone comprises one or more electrically conductive layers and the second zone comprises at least one additional electrically conductive layer.
29 . The power stage assembly of claim 27 , wherein the first zone comprises a single electrically conductive layer and the second zone comprises a plurality of electrically conductive layers.
30 . The power stage assembly of claim 28 , wherein the layer structures of the first and second zones comprise a dielectric core, a top conductive layer and a bottom conductive layer, and wherein the dielectric core of the first zone comprises an inlay of a material having a lower thermal resistance than the dielectric core of the second zone.
31 . The power stage assembly of claim 30 , wherein the second zone comprises at least one intermediate conductive layer between the top conductive layer and the bottom conductive layer.
32 . The power stage assembly of claim 30 , wherein the second zone comprises a plurality of intermediate conductive layers and dielectric layers between the top conductive layer and the bottom conductive layer.
33 . The power stage assembly of claim 28 , wherein the conductive layers of the first zone are configured for a semiconductor power switching device comprising a half-bridge switch topology, each high-side switch and low-side switch of the half-bridge comprising one transistor switch or a plurality of transistor switches connected in parallel; and conductive layers of the second zone are configured for driver components for the high-side and the low-side switches.
34 . The power stage assembly of claim 28 , wherein the conductive layers of the first zone are configured for a semiconductor power switching device comprising a full-bridge switch topology, each high-side switch and low-side switch of the full-bridge comprising one transistor switch or a plurality of transistor switches connected in parallel; and conductive layers of the second zone are configured for driver components for the high-side and the low-side switches.
35 . The power stage assembly of claim 28 , wherein the conductive layers of the first zone are configured for a semiconductor power switching device comprising a single switch topology comprising one transistor switch or a plurality of transistor switches connected in parallel; and conductive layers of the second zone are configured for driver components of the single switch.
36 . The power stage assembly of claim 28 , wherein the substrate is mounted on a heatsink.
37 . The power stage assembly of claim 36 , wherein the at least one bottom-cooled semiconductor power switching device has dual-side thermal pads, and a secondary heatsink is provided on a top side of said semiconductor power switching device.