Semiconductor memory devices and methods of manufacturing thereof
View Patent ↗A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.
1 . A memory device, comprising:
a plurality of first memory strings vertically extending through a first stack of alternately arranged first word lines (WLs) and first insulation layers, wherein each of the plurality of first memory strings comprises a plurality of first memory cells vertically spaced apart from one another;
a plurality of first bit lines (BLs) and a plurality of first source lines (SLs) that each vertically extend along a respective one of the first memory strings; and
a first seal ring structure that laterally encloses the plurality of first memory strings but is separated apart from the first stack;
wherein the plurality of first BLs, the plurality of first SLs, and the first seal ring structure are formed of a same material.
2 . The memory device of claim 1 , wherein the plurality of first SLs, the plurality of first BLs, and the first seal ring structure each essentially consist of a continuously formed metal material.
3 . The memory device of claim 1 , wherein the plurality of first SLs, the plurality of first BLs, and the first seal ring structure each essentially consist of a continuously formed semiconductor material.
4 . The memory device of claim 1 , further comprising:
a plurality of second memory strings vertically extending through a second stack of alternately arranged second WLs and second insulation layers, wherein each of the plurality of second memory strings comprises a plurality of second memory cells vertically spaced apart from one another; and
a plurality of second BLs and a plurality of second SLs that each vertically extend along a respective one of the second memory strings.
5 . The memory device of claim 4 , wherein at least the first WLs, the first BLs, the first SLs, and the first memory strings form a first memory array, and at least the second WLs, the second BLs, the second SLs, and the second memory strings form a second memory array.
6 . The memory device of claim 5 , wherein the first seal ring structure laterally encloses both of the first memory array and the second memory array.
7 . The memory device of claim 5 , further comprising a second seal ring laterally enclosing the first seal ring, with the first seal ring laterally enclosing both of the first memory array and the second memory array.
8 . The memory device of claim 5 , further comprising a second seal ring laterally enclosing the second memory array.
9 . The memory device of claim 1 , wherein the first WLs each extend along a direction, and a pair of the first BLs and first SLs corresponding to a respective one of the first memory strings are spaced from each other along the direction.
10 . The memory device of claim 1 , further comprising:
a plurality of memory films, each of the plurality of memory films surrounding one or more pairs of the first BLs and first SLs.
11 . A memory device, comprising:
a plurality of first memory strings vertically extending through a first stack of alternately arranged first word lines (WLs) and first insulation layers, wherein each of the plurality of first memory strings comprises a plurality of first memory cells vertically spaced apart from one another;
a plurality of first bit lines (BLs) and a plurality of first source lines (SLs) that each vertically extend along a respective one of the first memory strings; and
a first seal ring structure that laterally encloses the plurality of first memory strings but is separated apart from the first stack;
wherein the plurality of first BLs, the plurality of first SLs, and the first seal ring structure are formed of a continuously formed material.
12 . The memory device of claim 11 , further comprising:
a plurality of second memory strings vertically extending through a second stack of alternately arranged second WLs and second insulation layers, wherein each of the plurality of second memory strings comprises a plurality of second memory cells vertically spaced apart from one another; and
a plurality of second BLs and a plurality of second SLs that each vertically extend along a respective one of the second memory strings.
13 . The memory device of claim 12 , wherein at least the first WLs, the first BLs, the first SLs, and the first memory strings form a first memory array, and at least the second WLs, the second BLs, the second SLs, and the second memory strings form a second memory array.
14 . The memory device of claim 13 , wherein the first seal ring structure laterally encloses both of the first memory array and the second memory array.
15 . The memory device of claim 13 , further comprising a second seal ring laterally enclosing the first seal ring, with the first seal ring laterally enclosing both of the first memory array and the second memory array.
16 . The memory device of claim 13 , further comprising a second seal ring laterally enclosing the second memory array.
17 . The memory device of claim 11 , wherein the first WLs each extend along a direction, and a pair of the first BLs and first SLs corresponding to a respective one of the first memory strings are spaced from each other along the direction.
18 . The memory device of claim 11 , further comprising:
a plurality of memory films, each of the plurality of memory films surrounding one or more pairs of the first BLs and first SLs.
19 . A memory device, comprising:
a plurality of memory strings vertically extending through a stack of alternately arranged word lines (WLs) and insulation layers, wherein each of the plurality of memory strings comprises a plurality of memory cells vertically spaced apart from one another;
a plurality of bit lines (BLs) and a plurality of source lines (SLs) that each vertically extend along a respective one of the memory strings; and
a seal ring structure that laterally encloses the plurality of memory strings but is separated apart from the stack;
wherein the plurality of BLs, the plurality of SLs, and the seal ring structure are formed of a continuously formed material, and wherein the material is a metal material or a semiconductor material.
20 . The memory device of claim 19 , wherein the WLs each extend along a direction, and a pair of the BLs and SLs corresponding to a respective one of the memory strings are spaced from each other along the direction.