Semiconductor wafer including monitoring pattern structure with cover pattern layer and contact patterns disposed over monitoring pattern structure
A semiconductor wafer according to an embodiment includes a monitoring pattern structure disposed over a substrate, a cover pattern layer covering portions of the monitoring pattern structure over the substrate, and contact patterns disposed over the cover pattern layer to extend over the cover pattern layer.
1 . A semiconductor wafer comprising:
a monitoring pattern structure disposed over a substrate;
a cover pattern layer covering portions of the monitoring pattern structure over the substrate, the cover pattern layer including a hole pattern that selectively exposes the monitoring pattern structure;
an insulating layer disposed over the substrate, and contacting the exposed portion of the monitoring pattern structure through the hole pattern; and
contact patterns disposed over the cover pattern layer to extend over the cover pattern layer,
wherein the cover pattern layer comprises a conductive material.
2 . The semiconductor wafer of claim 1 , wherein the hole pattern has a plane shape of a circle, an ellipse, or a polygon.
3 . The semiconductor wafer of claim 1 , wherein the cover pattern layer is disposed along an edge of the monitoring pattern structure.
4 . The semiconductor wafer of claim 1 , wherein the monitoring pattern structure is disposed in a scribe lane region positioned between a plurality of chip regions of the substrate.
5 . The semiconductor wafer of claim 4 , wherein the cover pattern layer includes a trench pattern that extends in a direction substantially perpendicular to a width direction of the scribe lane region.
6 . The semiconductor wafer of claim 4 , wherein the cover pattern layer includes a recess formed in a portion of the cover pattern layer along a direction substantially perpendicular to the width direction of the scribe lane region.
7 . The semiconductor wafer of claim 6 , wherein a width of the cover pattern layer in the portion where the recess is formed is smaller than a width of the cover pattern layer in other portions where the recess is not formed.
8 . The semiconductor wafer of claim 4 , wherein the contact patterns include pillar structures disposed on an upper surface of the cover pattern layer and arranged along a direction substantially perpendicular to a width direction of the scribe lane region.
9 . The semiconductor wafer of claim 4 , wherein the contact patterns include wall structures disposed on an upper surface of the cover pattern layer and extending in a direction substantially perpendicular to a width direction of the scribe lane region.
10 . The semiconductor wafer of claim 1 , further comprising a connection pattern layer disposed on a surface over the cover pattern layer to cover the contact patterns.
11 . The semiconductor wafer of claim 10 ,
wherein the cover pattern layer includes nitride of a first metal,
wherein the contact pattern includes the first metal, and
wherein the connection pattern layer includes a second metal that is different from the first metal.
12 . A semiconductor wafer comprising:
a monitoring pattern structure disposed in a scribe lane region disposed between chip regions over a substrate;
a cover pattern layer covering a portion of the monitoring pattern structure disposed over the substrate, the cover pattern layer including hole patterns or trench patterns that selectively expose the monitoring pattern structure;
an insulating layer disposed over the substrate, and contacting the exposed portion of the monitoring pattern structure through the hole patterns; and
a stress alleviation structure including contact patterns disposed on the cover pattern layer to extend over the cover pattern layer, and
wherein the cover pattern layer comprises a conductive material.
13 . The semiconductor wafer of claim 12 , wherein the cover pattern layer is disposed along an edge of the monitoring pattern structure.
14 . The semiconductor wafer of claim 13 , wherein the cover pattern layer includes a recess formed along a direction substantially perpendicular to a width direction of the scribe lane region.
15 . The semiconductor wafer of claim 12 , wherein the contact patterns include pillar structures disposed on an upper surface of the cover pattern layer and arranged along a direction substantially perpendicular to a width direction of the scribe lane region.
16 . The semiconductor wafer of claim 12 , wherein the contact patterns include wall structures disposed on an upper surface of the cover pattern layer and extending in a direction substantially perpendicular to a width direction of the scribe lane region.
17 . The semiconductor wafer of claim 12 , wherein the stress alleviation structure further includes a connection pattern layer covering the contact patterns over the cover pattern layer.
18 . A semiconductor wafer comprising:
a monitoring pattern structure disposed in a scribe lane region positioned between a plurality of chip regions of a substrate;
a cover pattern layer disposed over an edge of the monitoring pattern structure, and including a hole pattern selectively exposing a portion of the monitoring pattern structure;
an insulating layer disposed over the substrate, and contacting the exposed portion of the monitoring pattern structure through the hole pattern; and
contact patterns disposed over the cover pattern layer, and
wherein the cover pattern layer comprises a conductive material.