Semiconductor package having a package substrate including a first area and a second area and method of fabricating the same
A semiconductor package includes a first package substrate having a first area and a second area that is distinct and separate from the first area, a first connection element disposed on the first area and having a first thickness, a first semiconductor chip connected to the first connection element, a second connection element disposed on the second area and having a second thickness that is greater than the first thickness, a third connection element disposed on the second connection element and electrically connected to the second connection element, a second package substrate disposed on the third connection element, and a second semiconductor chip disposed on the second package substrate.
1 . A semiconductor package comprising:
a first package substrate having a first area and a second area that is distinct and separate from the first area;
a first connection element disposed on the first area and having a first thickness;
a first semiconductor chip connected to the first connection element;
a second connection element disposed on the second area and having a second thickness that is greater than the first thickness;
a third connection element disposed on the second connection element and electrically connected to the second connection element;
a second package substrate disposed on the third connection element; and
a second semiconductor chip disposed on the second package substrate.
2 . The semiconductor package of claim 1 , further comprising a first mold film configured to cover a side surface of the first semiconductor chip, cover a side surface of the second connection element, and expose an upper surface of the second connection element.
3 . The semiconductor package of claim 2 , wherein the upper surface of the second connection element is coplanar with an upper surface of the first mold film that covers the side surface of the second connection element.
4 . The semiconductor package of claim 2 , wherein an upper surface of the first semiconductor chip is exposed by the first mold film.
5 . The semiconductor package of claim 4 , further comprising a second mold film formed on the second package substrate and configured to cover the second semiconductor chip, wherein an upper surface of the second mold film is coplanar with the upper surface of the first semiconductor chip exposed by the first mold film.
6 . The semiconductor package of claim 1 , wherein the first semiconductor chip is an Application Processor (AP), and the second semiconductor chip is a memory chip.
7 . A semiconductor package comprising:
a first package substrate having a first area and a second area that is distinct and separate from the first area;
a first semiconductor chip disposed on the first area;
a first connection element disposed on the second area;
a mold film configured to cover at least a part of the first semiconductor chip and the first connection element and expose an upper surface of the first connection element;
a second package substrate on the first connection element; and
a second semiconductor chip on the second package substrate.
8 . The semiconductor package of claim 7 , wherein the mold film covers a side surface of the first semiconductor chip and does not cover an upper surface of the first semiconductor chip.
9 . The semiconductor package of claim 7 , wherein the mold film covers a side surface of the first connection element.
10 . The semiconductor package of claim 9 , wherein an upper surface of the mold film covering the side surface of the first connection element is coplanar with the upper surface of the first connection element.
11 . The semiconductor package of claim 7 , further comprising a second connection element,
wherein the second package substrate is in contact with the first connection element, and
wherein the second connection element is disposed on a lower surface of the second package substrate.
12 . The semiconductor package of claim 11 , wherein the first connection element and the second connection element enable a signal to be exchanged between the first semiconductor chip and the second semiconductor chip.
13 . The semiconductor package of claim 7 , further comprising a second connection element configured to connect the first semiconductor chip to the first package substrate,
wherein a thickness of the first connection element is greater than a thickness of the second connection element.
14 . A method of fabricating a semiconductor package, comprising:
forming a first semiconductor chip in a first area of a first package substrate;
forming a first connection element in a second area of the first package substrate that is distinct and separate from the first area;
forming a mold film to cover the first semiconductor chip and the first connection element; and
grinding a part of the mold film that covers an upper surface of the first connection element to expose the upper surface of the first connection element while grinding a part of the first connection element.
15 . The method of claim 14 , wherein when a thickness of the first connection element before the grinding is A and a thickness of the first connection element after the grinding is B, B/A is greater than or equal to 1/100.
16 . The method of claim 15 , wherein the thickness of the first connection element after grinding is 10 microns (μm) or more.
17 . The method of claim 14 , further comprising forming a second semiconductor chip on the first connection element, wherein the second semiconductor chip is disposed on a second package substrate.
18 . The method of claim 17 , further comprising forming a second connection element on a lower surface of the second package substrate.
19 . The method of claim 18 , further comprising connecting the first connection element and the second connection element using a reflow process.