Semiconductor assemblies with systems and methods for using an interchangeable interposer to connect die to common substrate
Semiconductor device assemblies having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device assembly includes a substrate, a controller, and an interposer. The substrate has a top surface and a bottom surface. A cavity extends below the top surface. The controller has a first pin-out pattern. The interposer has a top surface with the first pin-out pattern that is directly connected to the controller and a bottom surface that has a second pin-out pattern. The interposer interconnects the first and second pin-out patterns, and the interposer and the second pin-out pattern are configured to be directly attached to a surface of the substrate in the cavity.
1 . A semiconductor device assembly, comprising:
a substrate having atop surface and a bottom surface, first and second layers of prepreg disposed between the top and bottom surfaces, the first layer of prepreg being disposed closer to the top surface than the second layer of prepreg, and a core layer disposed between the first and second layers of prepreg, the substrate further comprising a cavity extending from the top surface to an intermediate depth between the top surface and the bottom surface, the cavity having an intermediate surface vertically aligned with an interface between the first layer of prepreg and the core layer;
a controller having a first pin-out pattern; and
an interposer having a top surface with the first pin-out pattern that is directly attached to the controller and a bottom surface having a second pin-out pattern, the interposer interconnecting at least a portion of the first and second pin-out patterns,
wherein the interposer is configured to be directly attached to the intermediate surface of the substrate in the cavity at the intermediate depth,
wherein the interposer has a first length less than a second length of the cavity such that a gap extends between a side edge of the interposer and a facing sidewall of the cavity, and
wherein the second pin-out pattern of the interposer is directly attached to corresponding electrical contacts on the intermediate surface of the substrate having the second pin-out pattern.
2 . The semiconductor device assembly of claim 1 , wherein the bottom surface of the interposer is disposed entirely within the cavity.
3 . The semiconductor device assembly of claim 1 , wherein the first and second pin-out patterns are different patterns.
4 . The semiconductor device assembly of claim 1 , wherein the interposer is further configured to redistribute the first pin-out pattern to the second pin-out pattern, and wherein the second pin-out pattern has a different pitch than the first pin-out pattern.
5 . The semiconductor device assembly of claim 1 , wherein the interposer is further configured to redistribute the first pin-out pattern to only a portion of the second pin-out pattern.
6 . The semiconductor device assembly of claim 1 , wherein the interposer comprises an embedded trace substrate.
7 . The semiconductor device assembly of claim 1 , wherein the interposer further comprises at least one via.
8 . The semiconductor device assembly of claim 1 , wherein the interposer has a larger footprint than a footprint of the controller.
9 . The semiconductor device assembly of claim 1 , wherein the electrical contacts on the surface of the substrate comprise a micro-ball array.
10 . A semiconductor device assembly, comprising:
a substrate having a top surface and a bottom surface, first and second layers of prepreg disposed between the top and bottom surfaces, the first layer of prepreg being disposed closer to the top surface than the second layer of prepreg, and a core layer disposed between the first and second layers of prepreg, the substrate further comprising a cavity extending into the substrate from the top surface, the cavity having an intermediate surface vertically aligned with an interface between the first layer of prepreg and the core layer;
a controller having a first pin-out pattern;
an interposer having a top surface with the first pin-out pattern that is connected to the controller and a bottom surface having a second pin-out pattern, the interposer interconnecting the first and second pin-out patterns, wherein the second pin-out pattern of the interposer is directly attached to the intermediate surface of the substrate in the cavity;
at least one memory die attached to the top surface of the substrate; and
mold material at least partially encapsulating the top surface of the substrate, the controller, the interposer, and the at least one memory die,
wherein the interposer has a first length less than a second length of the cavity such that a gap extends between a side edge of the interposer and a facing sidewall of the cavity.
11 . The semiconductor device assembly of claim 10 , wherein the interposer comprises an embedded trace substrate.
12 . The semiconductor device assembly of claim 10 , wherein the first and second pin-out patterns are different.
13 . The semiconductor device assembly of claim 10 , wherein the interposer comprises prepreg.
14 . The semiconductor device assembly of claim 1 , wherein a mold material is disposed in the gap.
15 . The semiconductor device assembly of claim 10 , wherein a mold material is disposed in the gap.