Semiconductor package and method of manufacturing the semiconductor package
A method of manufacturing a semiconductor package including forming a first semiconductor chip including a first substrate having a first and second surfaces and forming a second semiconductor chip including a second substrate having third and fourth surfaces. Arranging the second semiconductor chip on the first semiconductor chip such that bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip. Forming a first through via having a first diameter and that penetrates the first substrate. Forming an insulating layer that exposes a first end of the first through via on the second surface of the first substrate, etching the first end of the first through via to a first depth, and applying a conductive material to the first end to form the conductive pad having a second diameter.
1 . A method of manufacturing a semiconductor package, the method comprising:
forming a first semiconductor chip including a first substrate, the first substrate having first and second surfaces opposite to each other;
forming a second semiconductor chip including a second substrate, the second substrate having third and fourth surfaces opposite to each other; and
arranging the second semiconductor chip on the first semiconductor chip such that a front surface of the second semiconductor chip faces a rear surface of the first semiconductor chip, and bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip,
wherein the forming the first semiconductor chip includes,
forming a first through via that penetrates the first substrate from an activation layer that is formed on the first surface of the first substrate, the first through via having a first diameter;
forming a first insulating layer that exposes a first end of the first through via on the second surface of the first substrate;
etching the first end of the first through via that is exposed from an outer surface of the first insulating layer to a first depth; and
applying a conductive material on the first end of the first through via to form a first conductive pad that is included among the conductive pads, the first conductive pad having a second diameter.
2 . The method of claim 1 , wherein the forming the second semiconductor chip includes,
forming a second through via that penetrates the second substrate from an activation layer formed on the third surface of the second substrate, the second through via having a third diameter;
forming a second insulating layer that exposes a first end of the second through via on the third surface of the second substrate;
etching the first end of the second through via that is exposed from an outer surface of the second insulating layer to a second depth; and
applying the conductive material on the first end of the second through via to form a second conductive pad that has a fourth diameter.
3 . The method of claim 2 , wherein a bonding pad included among the bonding pads of the second semiconductor chip has a fifth diameter that is greater than the second diameter of the first conductive pad.
4 . The method of claim 3 , wherein the second diameter of the first conductive pad is within a range of 2 μm to 6 μm, and
the fifth diameter of the bonding pad is within a range of 6 μm to 10 μm.
5 . The method of claim 1 , wherein the forming the first semiconductor chip further includes,
forming a plurality of cavities on the outer surface of the first insulating layer; and
filling up the plurality of cavities with the conductive material to form a plurality of dummy pads.
6 . The method of claim 5 , wherein the forming the plurality of cavities includes,
forming the plurality of cavities from the outer surface of the first insulating layer to have a third depth that is equal to the first depth.
7 . The method of claim 1 , wherein the forming the first through via includes,
forming the first through via such that the first end of the first through via protrudes from the second surface of the first substrate, and
the forming the first insulating layer includes,
forming the first insulating layer on the second surface of the first substrate to cover the first through via; and
polishing the first insulating layer to expose the first end of the first through via.
8 . The method of claim 1 , wherein the etching the first end of the first through via includes etching through etchant that has an etching selectivity with respect to the first through via.
9 . The method of claim 1 , wherein the conductive material includes at least one of nickel (Ni), antimony (Sb), bismuth (Bi), zinc (Zn), indium (In), palladium (Pd), platinum (Pt), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), gold (Au), silver (Ag), chromium (Cr), and tin (Sn).
10 . The method of claim 1 , wherein the first end of the first through via is etched such that the first end of the first through via is below a top surface of the first insulating layer.
11 . A semiconductor package, comprising:
a first semiconductor chip having a first front surface and a first rear surface opposite to each other; and
a second semiconductor chip having a second front surface that is bonded to the first rear surface of the first semiconductor chip, the second semiconductor chip having bonding pads that are exposed from the second front surface,
wherein the first semiconductor chip includes,
a first substrate having a first surface, and a second surface opposite to the first surface;
a circuit layer provided on the first surface of the first substrate;
a first through via extending to penetrate through the first substrate, the first through via having a first diameter;
a first insulating layer partially covering the first through via on the second surface of the first substrate, the first insulating layer having a first opening that has a first depth from an outer surface of the first insulating layer, the first opening having a bottom surface that exposes a first end of the first through via; and
a first conductive pad, having a second diameter, provided on the exposed first end of the first through via in the first opening of the first insulating layer, the first conductive pad bonded to a bonding pad included among the bonding pads of the second semiconductor chip.
12 . The semiconductor package of claim 11 , wherein the second semiconductor chip includes,
a second substrate having a third surface, and a fourth surface opposite to the third surface;
a second circuit layer provided on the third surface of the second substrate;
a second through via extending to penetrate through the second substrate, the second through via having a third diameter;
a second insulating layer covering the second through via on the fourth surface of the second substrate;
the second insulating layer having a second opening that has a second depth from an outer surface of the second insulating layer, the second opening having a bottom surface that exposes a first end of the second through via; and
a second conductive pad, having a fourth diameter, provided on the exposed first end of the second through via in the second opening of the second insulating layer.
13 . The semiconductor package of claim 12 , wherein the bonding pad of the second semiconductor chip has a fifth diameter that is greater than the second diameter of the first conductive pad.
14 . The semiconductor package of claim 13 , wherein the second diameter of the first conductive pad is equal to the first diameter of the first through via.
15 . The semiconductor package of claim 13 , wherein the second diameter of the first conductive pad is within a range of 2 μm to 6 μm, and
the fifth diameter of the bonding pad is within a range of 6 μm to 10 μm.
16 . The semiconductor package of claim 11 , wherein the first semiconductor chip further includes a plurality of dummy pads that are provided within the first insulating layer, the plurality of dummy pads being exposed from the first rear surface.
17 . The semiconductor package of claim 16 , wherein the first conductive pad has a first thickness, and
each of the plurality of dummy pads has a second thickness that is equal to the first thickness.
18 . The semiconductor package of claim 11 , wherein the first through via includes a first metal material, and
the first conductive pad includes a second metal material that is different from the first metal material.
19 . The semiconductor package of claim 11 , wherein the first conductive pad is in contact with and directly bonded to a bonding pad included among the bonding pads of the second semiconductor chip.
20 . A method of manufacturing a semiconductor package, comprising:
forming a first semiconductor chip including a first substrate, the first substrate having first and second surfaces opposite to each other;
forming a second semiconductor chip including a second substrate, the second substrate having third and fourth surfaces opposite to each other; and
arranging the second semiconductor chip on the first semiconductor chip such that a front surface of the second semiconductor chip faces a rear surface of the first semiconductor chip, and bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip,
wherein the forming the first semiconductor chip includes,
forming a first through via that penetrates the first substrate from an activation layer formed on the first surface of the first substrate, the first through via having a first diameter;
forming a first insulating layer that exposes a first end of the first through via on the second surface of the first substrate;
etching the first end of the first through via that is exposed from an outer surface of the first insulating layer to a first depth;
forming a plurality of first cavities in the outer surface of the first insulating layer; and
applying a conductive material on the first end of the first through via to form a first conductive pad that is included among the conductive pads, the first conductive pad having a second diameter equal to the first diameter and on the plurality of first cavities to form a plurality of dummy pads,
wherein the forming the second semiconductor chip includes,
forming a second through via that penetrates the second substrate from the bonding pads formed on the third surface of the second substrate, the second through via having a third diameter;
forming a second insulating layer that exposes a first end of the second through via on the fourth surface of the second substrate;
etching the first end of the second through via that is exposed from an outer surface of the second insulating layer to a second depth;
forming a plurality of second cavities on the outer surface of the second insulating layer; and
applying the conductive material on the first end of the second through via to form a second conductive pad that has a fourth diameter equal to the third diameter and on the second cavities to form a plurality of second dummy pads.