Integrated circuit package with multi-layered metallization lines including a copper layer on a non-copper seed layer
IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.
1 . An integrated circuit (IC) device package, comprising:
a substrate comprising a dielectric material; and
a first metallization level comprising a plurality of metallization lines extending over the dielectric material, wherein each of the metallization lines comprises:
a first layer of predominantly a first metal that is other than Cu, the first layer extending a first line length over the dielectric material, having a first thickness over the dielectric material of at least 100 nm; and
a second layer on the first layer, wherein the second layer is a second metal that is predominantly Cu, the second layer extending at least the first line length over the dielectric material and having a second thickness over the first layer that is at least twice the first thickness.
2 . The IC device package of claim 1 , wherein the first layer is continuous over the first line length of each of the metallization lines.
3 . The IC device package of claim 1 , wherein the first metal is at least one of Pd, Ru, Pt, Ti, or Au.
4 . The IC device package of claim 3 , wherein the first metal is Pd or Ru.
5 . The IC device package of claim 4 , wherein the first metal is Ru.
6 . The IC device package of claim 1 , wherein each of the metallization lines is to electrically interconnect a first IC die to a laterally adjacent second IC die, wherein the metallization level comprises a plurality of metallization vias, wherein individual ones of the metallization vias are on a portion of corresponding ones of the metallization lines, and wherein the metallization vias are of the second metal.
7 . The IC device package of claim 1 , wherein:
the first layer has a first line width,
the second layer has a second line width;
the first line length is shorter than the second line length by an amount of lateral undercut by which the first line width is also narrower than the second line width; and
the amount of lateral undercut is at least equal to first thickness.
8 . The IC device package of claim 1 , wherein the first layer has columnar grain texture oriented normal to a plane of the substrate.
9 . The IC device package of claim 1 , wherein each of the metallization lines further comprises a third layer between the dielectric material and the first layer of the metallization line, the third layer comprising a third metal, different than the first or second metals.
10 . The IC device package of claim 9 , wherein the third layer comprises at least one of Ti, Pd, Ru, Pt, Au, Sn, Ag, W or nitrogen.
11 . The IC device package of claim 1 , wherein:
the device package further comprises a second metallization level between the first metallization level and the substrate; and
the second metallization level comprises a second plurality of metallization lines comprising other than the first metal.
12 . The IC device package of claim 11 , wherein all material layers of each of the metallization lines of the second metallization level comprise predominantly Cu.
13 . The IC device package of claim 12 , wherein one or more surfaces of each of the metallization lines of the first metallization level have a lower average roughness (Ra) than one or more surfaces of each of the metallization lines of the second metallization level.
14 . A system comprising:
a first integrated circuit (IC) die;
a second IC die; and
an integrated circuit (IC) device package having a first side coupled to both of the first IC die and the second IC die and a second side coupled to a host component, the IC device package comprising a metallization line interconnecting the first IC die with the second IC die, and the metallization line comprising:
a first layer at least partially over a dielectric material, wherein the first layer comprises predominantly Pd, Ru, Pt, Ti, or Au and has a first thickness over the dielectric material of at least 500 nm; and
a second layer in contact with the first layer, wherein the second layer comprises predominantly Cu, and has a second thickness over the dielectric material that is at least 1 μm.
15 . The system of claim 14 , wherein:
the system further comprises a power supply coupled to the IC device package through an interconnect interface between the IC device package and the host component.
16 . The system of claim 14 , wherein:
the first thickness is at least 500 nm; and
the second thickness is 3-15 μm.
17 . A method of fabricating an integrated circuit (IC) device package, the method comprising:
receiving a substrate comprising a dielectric material;
depositing a first material layer to a first thickness of at least 100 nm over the dielectric material, wherein the first material layer comprises predominantly Pd, Ru, Pt, Ti, or Au;
forming a line metallization by electrolytically plating, to a second thickness, a second material layer on a first portion the first material layer, wherein the second thickness is at least twice the first thickness and the second material layer comprises predominantly Cu; and
delineating the line metallization by removing a second portion of the first material layer with an etch process that is selective to the first material layer relative to the second material layer, the etch process laterally undercutting an edge portion of the second material layer by at least the first thickness.
18 . The method of claim 17 , wherein:
depositing the first material layer comprises sputter depositing the Pd, Ru, Pt, Ti, or Au to have a columnar grain texture oriented normal to a plane of the substrate.
19 . The method of claim 17 , wherein the method comprises masking the second portion of the first material layer with a photodefinable material that is developed to expose the first portion of the first material layer within an opening of the photodefinable material.