Semiconductor package

1 . A semiconductor package comprising:

a semiconductor chip having a first surface and a second surface opposite to the first surface;

a lower redistribution structure disposed on the first surface of the semiconductor chip;

conductive connection members disposed on the lower redistribution structure so as to be outside the semiconductor chip;

an upper redistribution structure disposed on the second surface of the semiconductor chip;

a plurality of first conductive pads disposed on the upper redistribution structure to be spaced apart from each other; and

a plurality of second conductive pads disposed on the upper redistribution structure to be connected with each other,

wherein the upper redistribution structure comprises:

an upper redistribution insulating layer disposed on the second surface of the semiconductor chip;

a first upper redistribution line extending in a horizontal direction inside the upper redistribution insulating layer;

a plurality of first upper redistribution vias extending in a vertical direction inside the upper redistribution insulating layer, each of the plurality of first upper redistribution vias contacting an upper surface of the first upper redistribution line and connecting a corresponding one of the plurality of first conductive pads to the first upper redistribution line;

a pad line extending on the upper redistribution insulating layer, and directly connecting a first one of the plurality of second conductive pads with a second one of the plurality of second conductive pads; and

a pad via extending in the vertical direction inside the upper redistribution insulating layer from a first one of the plurality of first conductive pads to a first one of the conductive connection members, and connecting the first one of the plurality of first conductive pads to the first one of the conductive connection members,

wherein each of the plurality of first conductive pads, the plurality of second conductive pads, and the pad line are positioned at the same vertical level, and

wherein the semiconductor package further comprises a passivation layer disposed on an upper portion of the upper redistribution insulating layer and exposing at least a part of each of the plurality of first conductive pads and at least a part of each of the plurality of second conductive pads.

2 . The semiconductor package of claim 1 , further comprising:

a second upper redistribution line extending inside the upper redistribution insulating layer; and

a plurality of second upper redistribution vias extending in the vertical direction inside the upper redistribution insulating layer and connecting the second upper redistribution line to the plurality of second conductive pads, or connecting the second upper redistribution line to a second one of the conductive connection members.

3 . The semiconductor package of claim 2 ,

wherein the plurality of first conductive pads, the plurality of first upper redistribution vias, the first upper redistribution line, and the pad via are configured to provide a movement path of a data signal of the semiconductor chip, and

wherein the plurality of second conductive pads, the pad line, the plurality of second upper redistribution vias, and the second upper redistribution line are configured to provide a movement path of a power signal for an operation of the semiconductor chip, or are configured to provide a movement path of a ground signal for grounding the semiconductor chip.

4 . The semiconductor package of claim 2 ,

wherein the plurality of first conductive pads, the plurality of first upper redistribution vias, the first upper redistribution line, and the pad via are configured to provide a movement path of a data signal of the semiconductor chip, and

wherein the plurality of second conductive pads, the pad line, the plurality of second upper redistribution vias, and the second upper redistribution line are configured to provide a movement path of at least one of a command signal and an address signal of the semiconductor chip.

5 . The semiconductor package of claim 1 , wherein a lowermost surface of the pad via is at a lower level than a lower surface of the first upper redistribution line.

6 . The semiconductor package of claim 1 , wherein a thickness of the first upper redistribution line is greater than a thickness of each of the plurality of first conductive pads.

7 . The semiconductor package of claim 6 , wherein the thickness of each of the plurality of first conductive pads is in a range of 5 micrometers to 15 micrometers.

8 . The semiconductor package of claim 7 , wherein the thickness of the first upper redistribution line is greater than the thickness of each of the plurality of first conductive pads within a range of 7 micrometers to 40 micrometers.

9 . The semiconductor package of claim 1 , wherein the pad via is disposed to be spaced apart from the first upper redistribution line.

10 . The semiconductor package of claim 1 , further comprising:

a lower redistribution insulating layer on the first surface of the semiconductor chip;

a first lower redistribution line extending inside the lower redistribution insulating layer and connected to the first one of the conductive connection members; and

a second lower redistribution line extending inside the lower redistribution insulating layer and connected to the second one of the conductive connection members,

wherein the first lower redistribution line extends from below the first one of the conductive connection members to below the semiconductor chip, and

wherein the second lower redistribution line extends from below the second one of the conductive connection members to below the semiconductor chip.

11 . The semiconductor package of claim 1 , further comprising:

a plurality of external connection terminals disposed in a lower portion of the lower redistribution structure,

wherein at least one of the plurality of external connection terminals does not vertically overlap the semiconductor chip and is electrically connected to the second one of the conductive connection members.

12 . The semiconductor package of claim 1 , further comprising:

a plurality of base layers stacked on the lower redistribution structure in the vertical direction to surround the semiconductor chip; and

a cover insulating layer disposed in a space between the semiconductor chip and the plurality of base layers,

wherein the conductive connection members comprise:

a plurality of substrate lines disposed on at least one of upper and lower surfaces of the plurality of base layers; and

a plurality of second substrate vias passing through the plurality of base layers in the vertical direction and connecting the plurality of substrate lines.

13 . The semiconductor package of claim 1 , further comprising:

a molding layer surrounding the semiconductor chip on the lower redistribution structure,

wherein the conductive connection members comprise a conductive post passing through the molding layer in the vertical direction and connecting the lower redistribution structure to the upper redistribution structure.

14 . A semiconductor package comprising:

a semiconductor chip having a first surface and a second surface opposite to the first surface;

a lower redistribution structure disposed on the first surface of the semiconductor chip;

a substrate layer disposed on the lower redistribution structure and surrounding the semiconductor chip, and comprising a plurality of base layers stacked in a vertical direction;

a plurality of substrate lines disposed on at least one of upper and lower surfaces of the plurality of base layers;

a plurality of substrate vias passing through the plurality of base layers in the vertical direction and connecting the plurality of substrate lines;

an upper redistribution structure disposed on the second surface of the semiconductor chip;

a plurality of first conductive pads disposed on the upper redistribution structure to be spaced apart from each other; and

a plurality of second conductive pads on the upper redistribution structure to be connected with each other,

wherein the upper redistribution structure comprises:

an upper redistribution insulating layer on the second surface of the semiconductor chip;

a first upper redistribution line extending in a horizontal direction inside the upper redistribution insulating layer, overlapping the plurality of first conductive pads in the vertical direction, and connecting the plurality of first conductive pads to each other; and

a pad line extending on the upper redistribution insulating layer, and directly connecting a first one of the plurality of second conductive pads with a second one of the plurality of second conductive pads,

wherein each of the plurality of first conductive pads, the plurality of second conductive pads, and the pad line are positioned at the same vertical level, and

wherein the semiconductor package further comprises a passivation layer disposed on an upper portion of the upper redistribution insulating layer and exposing at least a part of each of the plurality of first conductive pads and at least a part of each of the plurality of second conductive pads.

15 . The semiconductor package of claim 14 , wherein a thickness of the first upper redistribution line is greater than a thickness of the pad line.

16 . The semiconductor package of claim 14 , wherein the upper redistribution structure comprises:

a plurality of first upper redistribution vias extending in the vertical direction inside the upper redistribution insulating layer and contacting an upper surface of the first upper redistribution line, each of the plurality of first upper redistribution vias connecting a corresponding one of the plurality of first conductive pads to the first upper redistribution line; and

a pad via extending in the vertical direction inside the upper redistribution insulating layer, and connecting a first one of the plurality of first conductive pads to the substrate lines of the substrate layer,

wherein an upper surface of the pad via contacts a lower surface of the first one of the plurality of first conductive pads, and

wherein a lower surface of the pad via is at a lower level than a lower surface of the first upper redistribution line.

17 . The semiconductor package of claim 16 , wherein the first one of the plurality of first conductive pads vertically overlaps the first upper redistribution line and the pad via.