Semiconductor package

1 . A circuit board comprising:

a substrate;

a first protective layer disposed on the substrate and including a first through hole; and

a second protective layer disposed inside the first through hole and spaced apart from the first protective layer in a horizontal direction and including a plurality of second through holes,

wherein the second protective layer includes a plurality of inner surfaces forming the plurality of second through holes, and an outer surface surrounding the plurality of inner surfaces,

wherein an inner surface forming the first through hole of the first protective layer and the outer surface of the second protective layer each include one surface facing each other in the horizontal direction, and

wherein a separation area between the one surface of the first protective layer and the one surface of the second protective layer includes a first separation area having a first width along the horizontal direction, and a second separation area having a second width different from the first width.

2 . The circuit board of claim 1 , wherein the first protective layer includes a plurality of third through holes disposed around the first through hole.

3 . The circuit board of claim 2 , wherein the at least some of the plurality of third through holes have a width greater than a width of the second through holes.

4 . The circuit board of claim 3 , wherein at least some of the plurality of third through holes include a post, and

wherein a thickness of the post in a vertical direction is thicker than a thickness of the second protective layer in the vertical direction.

5 . The circuit board of claim 1 , wherein the separation area is provided as a closed loop along the outer surface of the second protective layer.

6 . The circuit board of claim 1 , wherein at least a portion of one surface of the first protective layer and at least a portion of one surface of the second protective layer are parallel to each other.

7 . The circuit board of claim 1 , wherein the first width is greater than the second width.

8 . The circuit board of claim 7 , wherein one surface of the first protective layer includes a first protruding surface protruding toward the outer surface of the second protective layer, and

wherein the first protruding surface forms the second separation area.

9 . The circuit board of claim 7 , wherein one surface of the second protective layer includes a second protruding surface protruding toward the inner surface of the first protective layer, and

wherein the second protruding surface forms the second separation area.

10 . The circuit board of claim 7 , wherein the substrate includes a plurality of pads disposed on an upper surface of the substrate, and

wherein a number of pads vertically overlapping with the first separation area among the plurality of pads is greater than a number of pads vertically overlapping with the second separation area.

11 . The circuit board of claim 7 , wherein the separation area includes a third separation area having a third width smaller than the second width along the horizontal direction.

12 . The circuit board of claim 1 , wherein the substrate includes a first area vertically overlapping with the first protective layer, a second area vertically overlapping with the second protective layer, and a third area between the inner surface of the first protective layer and the outer surface of the second protective layer.

13 . The circuit board of claim 12 , wherein the substrate includes a plurality of pads and a plurality of traces disposed on an upper surface of the substrate,

wherein the plurality of pads includes a first pad portion disposed in the third area, the first pad portion having an exposed top surface, and

wherein the plurality of traces includes a first trace portion disposed in the third area, the first trace portion having an exposed top surface.

14 . The circuit board of claim 13 , wherein the plurality of pads include a second pad portion vertically overlapping the plurality of second through holes.

15 . The circuit board of claim 1 , wherein the inner surface of the first protective layer includes a first inner surface, a second inner surface facing the first inner surface, a third inner surface and a fourth inner surface disposed between the first inner surface and the second inner surface and facing each other,

wherein the outer surface of the second protective layer includes a first outer surface adjacent to the first inner surface, a second outer surface adjacent to the second inner surface, a third outer surface adjacent to the third inner surface, and a fourth outer surface adjacent to the fourth inner surface,

wherein the first inner surface of the first protective layer includes one surface of the first protective layer, and

wherein the first outer surface of the second protective layer includes one surface of the second protective layer.

16 . The circuit board of claim 15 , wherein the plurality of inner surfaces forming the plurality of second through holes are closed loops.

17 . A semiconductor package comprising:

a circuit board according to claim 15 ; and

a semiconductor device disposed on the second protective layer of the circuit board,

wherein the semiconductor device is electrically connected to a second pad portion of a plurality of pads disposed on an upper surface of the substrate.

18 . A circuit board comprising:

a substrate;

a first protective layer disposed on the substrate and including a first through hole; and

a second protective layer disposed inside the first through hole and spaced apart from the first protective layer in a horizontal direction and including a plurality of second through holes,

wherein the second protective layer includes a plurality of inner surfaces forming the plurality of second through holes, and an outer surface surrounding the plurality of inner surfaces,

wherein a separation area between an inner surface forming the first through hole of the first protective layer and the outer surface of the second protective layer is provided as a closed loop along the outer surface of the second protective layer,

wherein each of the inner surface of the first protective layer and the outer surface of the second protective layer are at least partially parallel to each other,

wherein the substrate includes an uppermost insulating layer, and a plurality of pads and a plurality of traces disposed on an upper surface of the uppermost insulating layer,

wherein the uppermost insulating layer includes a first region vertically overlapping with the first protective layer, a second region vertically overlapping with the second protective layer, and a third region between the inner surface of the first protective layer and the outer surface of the second protective layer, and

wherein first electrodes of the plurality of pads and the plurality of traces are disposed in the third region.

19 . The circuit board of claim 18 , wherein the inner surface of the first protective layer comprises a first inner surface, a second inner surface facing the first inner surface, a third inner surface, and a fourth inner surface,

wherein the third inner surface and the fourth inner surface are disposed between the first inner surface and the second inner surface and face each other, and

wherein the outer surface of the second protective layer comprises a first outer surface adjacent to the first inner surface, a second outer surface adjacent to the second inner surface, a third outer surface adjacent to the third inner surface and connected to the first outer surface and the second outer surface, and a fourth outer surface adjacent to the fourth inner surface and connected to the first outer surface and the second outer surface.

20 . The circuit board of claim 19 ,

wherein a third electrode of the plurality of pads is disposed in an area that vertically overlaps the plurality of second through holes of the second protective layer.

21 . The circuit board of claim 19 , wherein each of the first to fourth outer surfaces comprises a protruding edge or a concave edge toward an adjacent inner surface among the first to fourth inner surfaces.