Insulation layer for a semiconductor package
A semiconductor package includes an insulation layer provided between a molding compound and an electromagnetic interface (EMI) layer. The insulation layer covers an exposed portion of a bond wire that extends beyond a top surface of the molding compound due to a Z-height reduction of the molding compound. The insulation layer prevents a short from occurring between the bond wire and the EMI layer.
1 . A semiconductor package, comprising:
a substrate;
a molding compound covering a memory device communicatively coupled to the substrate by a bond wire, at least a portion of the bond wire extending past a top surface of the molding compound;
an insulation layer provided above the molding compound and covering the at least the portion of the bond wire that extends past the top surface of the molding compound; and
an electromagnetic interference (EMI) layer at least partially surrounding the substrate, the molding compound, and the insulation layer.
2 . The semiconductor package of claim 1 , wherein the insulation layer is approximately five micrometers (μm) thick.
3 . The semiconductor package of claim 1 , wherein the insulation layer is provided on an entire top surface of the molding compound.
4 . The semiconductor package of claim 1 , wherein the insulation layer is comprised of ink.
5 . The semiconductor package of claim 1 , wherein the insulation layer prevents a short from occurring between the EMI layer and the at least the portion of the bond wire that extends past the top surface of the molding compound.
6 . The semiconductor package of claim 1 , wherein the insulation layer enables a Z-height of the molding compound to be reduced by approximately forty-five micrometers (μm) or more.
7 . The semiconductor package of claim 1 , wherein the memory device is a NAND die stack.
8 . The semiconductor package of claim 1 , wherein the insulation layer comprises at least one of polyimide, parylene, silicon dioxide, and a polymer.
9 . A method for fabricating a semiconductor package, comprising:
coupling a NAND die stack and an associated bond wire to a surface of a substrate;
covering the NAND die stack and a first portion of the bond wire with a molding compound;
providing an insulation layer on a second portion of the bond wire, the second portion of the bond wire extending above a top surface of the molding compound; and
forming an electromagnetic interference (EMI) layer around at least a portion of the substrate, the insulation layer and the molding compound.
10 . The method of claim 9 , wherein the insulation layer is provided on the second portion of the bond wire using a one or more of a spraying process, a printing process and a sputtering process.
11 . The method of claim 9 , wherein the insulation layer is approximately five micrometers (μm) thick.
12 . The method of claim 9 , wherein the insulation layer is provided on an entire top surface of the molding compound.
13 . The method of claim 9 , wherein the insulation layer is comprised of ink.
14 . The method of claim 9 , wherein the insulation layer prevents a short from occurring between the EMI layer and the second portion of the bond wire.
15 . The method of claim 9 , wherein providing the insulation layer on the second portion of the bond wire comprises forming the insulation layer when the EMI layer is formed.
16 . A semiconductor package, comprising:
a substrate;
a memory device communicatively coupled to the substrate by a communication means;
a molding means covering the memory device and at least a first portion of the communication means;
an insulation means covering a second portion of the communication means that extends above a top surface of the molding means; and
an enclosure means at least partially surrounding the substrate, the molding means, and the insulation means.
17 . The semiconductor package of claim 16 , wherein the memory device is a NAND die stack.
18 . The semiconductor package of claim 16 , wherein the insulation means is approximately five micrometers (μm) thick.
19 . The semiconductor package of claim 16 , wherein the insulation means prevents a short from occurring between the enclosure means and the second portion of the communication means.
20 . The semiconductor package of claim 16 , wherein the insulation means is provided on an entire top surface of the molding means.