Three-dimensional fan-out memory package with conductive pillars and packaging method thereof
A three-dimensional fan-out memory package structure and a packaging method are disclosed. The package structure includes a three-dimensional fan-out memory package unit, which includes: a memory chip stack having at least two memory chips laminated in a stepped configuration, each memory chip is provided with a bonding pad; first metal connection pillars formed on the bonding pads; second metal connection pillars; a first encapsulating layer; a first rewiring layer formed on a back side of the memory chip stack; a second rewiring layer formed over a front side of the memory chip stack; and metal bumps. The package structure further includes: at least one peripheral circuit chip electrically connected with the first rewiring layer; and a second encapsulating layer, which encapsulates the peripheral circuit chip. The package structure allows for high-density and high-integration of line width/line spacing. The process time can be shortened, and the efficiency is high.
1 . A three-dimensional fan-out memory package structure, comprising:
a three-dimensional fan-out memory package unit, comprising:
a first memory chip and a second memory chip laminated in a stepped configuration, wherein the first memory chip and a first bonding layer under the first memory chip are stacked on a bottom of the stepped configuration, and the second memory chip and a second bonding layer under the second memory chip are stacked on a second step of the stepped configuration wherein the second step is arranged to be above and stepped out from the bottom step of the stepped configuration; wherein a first bonding pad is arranged on a surface of the first memory chip and a second bonding pad is arranged on a surface of the second memory chip on the stepped configuration;
a first rewiring layer having a first surface and a second surface, wherein the first surface of the first rewiring layer is bonded to the first bonding layer of the bottom step of the stepped configuration,
first metal connection pillars, wherein each of the first metal connection pillars has a first end and a second end, wherein the first end is formed on and electrically connected to one of the first and the second bonding pads;
second metal connection pillars, wherein the second metal connection pillars are formed outside the stepped configuration containing the first and second memory chips, and wherein each of the second metal connection pillars has a first end and a second end, each of the first ends is bonded to the first surface of the first rewiring layer;
a first encapsulating layer, wherein the first encapsulating layer encapsulates the first and the second memory chips in the stepped configuration, the first metal connection pillars, and the second metal connection pillars, wherein the second end of each of the first metal connection pillars and the second end of each of the second metal connection pillars are exposed from the first encapsulating layer;
a second rewiring layer having a first surface and a second surface, wherein the second surface of the second rewiring layer is formed over a top side of the stepped configuration, and and connected to the second end of each of the first metal connection pillars and the second end of each of the second metal connection pillars; and
metal bumps, formed on the first surface of the second rewiring layer;
at least one peripheral circuit chip arranged in two dimensions, wherein a back side of the at least one peripheral circuit chip is electrically connected with the second surface of the first rewiring layer, and
a second encapsulating layer, wherein the second encapsulating layer encapsulates the at least one peripheral circuit chip.
2 . The three-dimensional fan-out memory package structure according to claim 1 , wherein a bottom filler layer is provided between the back side of the at least one peripheral circuit chip and the second surface of the first rewiring layer.
3 . The three-dimensional fan-out memory package structure according to claim 1 , wherein in the memory chip stack, the first and second memory chips are laminated by the second bonding layer to stick together.
4 . The three-dimensional fan-out memory package structure according to claim 1 , wherein a material of the first metal connection pillars comprises at least one of gold, silver, aluminum, and copper, and wherein a material of the second metal connection pillars comprises at least one of gold, silver, aluminum, and copper.
5 . The three-dimensional fan-out memory package structure according to claim 1 , wherein a material of the bonding pad comprises metallic aluminum, a material of the first encapsulating layer comprises one of polyimide, silicone, and epoxy resin, and a material of the second encapsulating layer comprises one of polyimide, silicone, and epoxy resin.
6 . The three-dimensional fan-out memory package structure according to claim 1 , wherein each of the first rewiring layer and the second rewiring layer comprises a dielectric layer and a metal wiring layer, wherein a material of the dielectric layer of the first rewiring layer and the second rewiring layer comprises one or a combination of two or more of epoxy resin, silicone, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphorosilicate glass, and fluorine-containing glass, and a material of the metal wiring layer comprises one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
7 . The three-dimensional fan-out memory package structure according to claim 1 , wherein one of the metal bumps comprises a connecting structure, which includes a solder ball, or a metal pillar and a solder ball formed on the metal pillar, wherein the solder ball comprises one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball.
8 . A method of packaging a three-dimensional fan-out memory package structure, comprising:
providing a three-dimensional fan-out memory package unit, comprising:
forming a first memory chip and a second memory chip laminated in a stepped configuration, wherein the first memory chip and a first bonding layer under the first memory chip are stacked on a bottom of the stepped configuration, and the second memory chip and a second bonding layer under the second memory chip are stacked on a second step of the stepped configuration, wherein the second step is arranged to be above and stepped out from the bottom step of the stepped configuration;
forming a first bonding pad on a surface of the first memory chip and forming a second bonding pad on a surface of the second memory chip on the stepped configuration;
forming a first rewiring layer having a first surface and a second surface, wherein the first surface of the first rewiring layer is bonded to the first bonding layer of the bottom step of the stepped configuration;
forming first metal connection pillars, wherein each of the first metal connection pillars has a first end and a second end, wherein said first end is formed on and electrically connected to the one of the first and the second bonding pad;
forming second metal connection pillars, wherein each of the second metal connection pillars has a first end and a second end and is formed outside the memory chip stack;
forming second metal connection pillars, wherein the second metal connection pillars are formed outside the stepped configuration containing the first and second memory chips, and wherein each of the second metal connection pillars has a first end and a second end, each of the first ends of the second metal connection pillars is bonded to the first surface of the first rewiring layer;
forming a first encapsulating layer, wherein the first encapsulating layer encapsulates the first and the second memory chips in the stepped configuration the first metal connection pillars, and the second metal connection pillars, wherein the second end of each of the first metal connection pillars and the second end of each of the second metal connection pillars are exposed from the first encapsulating layer,
forming a second rewiring layer having a first surface and a second surface, wherein the second surface of the second rewiring layer is formed over a top side of the stepped configuration, and the second surface of the second rewiring layer is connected to a second end of each of the first metal connection pillars and the second end of each of the second metal connection pillars; and
forming metal bumps on the first surface of the second rewiring layer;
forming at least one peripheral circuit chip in two dimensions, wherein the at least one peripheral circuit chip is electrically connected with the second surface of the first rewiring layer; and
encapsulating the at least one peripheral circuit chip with a second encapsulating layer.
9 . The method of packaging the three-dimensional fan-out memory package structure according to claim 8 , wherein before encapsulating the at least one peripheral circuit chip using the second encapsulating layer, the method further comprises a step of forming a bottom filler layer between a back side of the at least one peripheral circuit chip and the second surface of the first rewiring layer.