Structure and formation method of package with integrated chips
A package structure and a formation method are provided. The method includes disposing a first chip structure over a carrier substrate. The first chip structure has a front-side interconnection structure facing the carrier substrate. The method also includes forming a back-side interconnection structure over the first chip structure. The first chip structure has a device portion between the back-side interconnection structure and the front-side interconnection structure. The back-side interconnection structure has stacked conductive vias. The method further includes bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding.
1 . A method for forming a package structure, comprising:
disposing a first chip structure over a carrier substrate, wherein the first chip structure has a front-side interconnection structure facing the carrier substrate;
forming a back-side interconnection structure over the first chip structure, wherein the first chip structure has a device portion between the back-side interconnection structure and the front-side interconnection structure, and the back-side interconnection structure has stacked conductive vias;
bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding, wherein the second chip structure is directly bonded to the front-side interconnection structure using dielectric-to-dielectric bonding and metal-to-metal bonding;
attaching a second carrier substrate to the back-side interconnection structure; and
removing the carrier substrate to expose the front-side interconnection structure before the second chip structure is bonded.
2 . The method for forming a package structure as claimed in claim 1 , further comprising:
directly bonding a third chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding, wherein bottommost surfaces of the third chip structure and the second chip structure are substantially level.
3 . The method for forming a package structure as claimed in claim 2 , wherein the third chip structure and the second chip structure are laterally spaced apart from each other.
4 . The method for forming a package structure as claimed in claim 2 , wherein a first distance between the first chip structure and the second chip structure is substantially equal to a second distance between the first chip structure and the third chip structure.
5 . The method for forming a package structure as claimed in claim 1 , further comprising:
removing the second carrier substrate to expose the back-side interconnection structure;
forming a redistribution structure on the back-side interconnection structure; and
forming conductive bumps over the redistribution structure.
6 . The method for forming a package structure as claimed in claim 1 , wherein the first chip structure is wider than the second chip structure.
7 . The method for forming a package structure as claimed in claim 1 , wherein the first chip structure is substantially as wide as the second chip structure.
8 . The method for forming a package structure as claimed in claim 7 , wherein the second chip structure is a semiconductor wafer.
9 . The method for forming a package structure as claimed in claim 1 , wherein the front-side interconnection structure is as wide as the back-side interconnection structure.
10 . The method for forming a package structure as claimed in claim 9 , wherein the front-side interconnection structure is formed after the device portion.
11 . A method for forming a package structure, comprising:
providing a semiconductor wafer, wherein the semiconductor wafer has a front-side interconnection structure, a device portion, and a back-side interconnection structure, the device portion is formed before the front-side interconnection structure is formed, and the device portion is between the front-side interconnection structure and the back-side interconnection structure;
performing a planarization process on one of the front-side interconnection structure and the back-side interconnection structure; and
bonding a chip structure to one of the front-side interconnection structure and the back-side interconnection structure using dielectric-to-dielectric bonding and metal-to-metal bonding after the planarization process.
12 . The method for forming a package structure as claimed in claim 11 , further comprising:
bonding a second chip structure to one of the front-side interconnection structure and the back-side interconnection structure using dielectric-to-dielectric bonding and metal-to-metal bonding, wherein bottommost surfaces of the chip structure and the second chip structure are substantially level; and
forming a dielectric layer laterally surrounding the chip structure and the second chip structure.
13 . The method for forming a package structure as claimed in claim 11 , wherein the chip structure is substantially as wide as the semiconductor wafer.
14 . The method for forming a package structure as claimed in claim 11 , further comprising:
forming a plurality of conductive vias in the back-side interconnection structure, wherein the conductive vias together form a via tower structure.
15 . The method for forming a package structure as claimed in claim 11 , wherein no conductive via completely penetrating through the device portion of the semiconductor wafer is formed.
16 . A method for forming a package structure, comprising:
providing a first chip-containing structure, wherein the first chip-containing structure has a front-side interconnection structure, a device portion, and a back-side interconnection structure, the device portion is between the front-side interconnection structure and the back-side interconnection structure, the front-side interconnection structure has a via tower structure having a stack of a plurality of conductive vias, and each of the conductive vias is thinner than the front-side interconnection structure;
performing a planarization process on one of the front-side interconnection structure and the back-side interconnection structure; and
bonding a second chip-containing structure to one of the front-side interconnection structure and the back-side interconnection structure using dielectric-to-dielectric bonding and metal-to-metal bonding after the planarization process.
17 . The method for forming a package structure as claimed in claim 16 , wherein the back-side interconnection structure has second stacked conductive vias.
18 . The method for forming a package structure as claimed in claim 16 , wherein the first chip-containing structure is wider than the second chip-containing structure.
19 . The method for forming a package structure as claimed in claim 16 , further comprising:
forming a protective layer over the first chip-containing structure to laterally surround the second chip-containing structure.
20 . The method for forming a package structure as claimed in claim 16 , wherein each of the conductive vias gradually shrinks along a direction towards the device portion.