IP Library › Granted Patent US 12677709
Granted Patent B2
US 12677709 · App. 18/405,005 · Granted Jul 7, 2026

Semiconductor device

Inventor: Tetsuo Yamashita (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H10W90/00H10W70/611H10W70/65H10W90/754
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Quick Facts
Patent No.
US 12677709
App. No.
18/405,005
Granted
Jul 7, 2026
Kind
B2
Abstract

An object of the present disclosure is to suppress reduction of noise resistance and parasitic oscillation in a semiconductor device. A semiconductor device includes: a plurality of semiconductor chips parallelly connected to each other; a source electrode; a first source pattern connected to the source electrode; a source sensing terminal; and a second source pattern connected to the source sensing terminal, wherein a surface of each of the semiconductor chips is connected to the first source pattern, a surface of a reference chip is connected to the second source pattern, a surface of at least one non-reference chip as the semiconductor chip other than the reference chip is not connected to the second source pattern, and a resistance value of a gate resistance of the reference chip is larger than a resistance value of a gate resistance of the non-reference chip.

Claims (24)

1 . A semiconductor device, comprising:

a plurality of semiconductor chips parallelly connected to each other;

a source electrode;

a first source pattern connected to the source electrode;

a source sensing terminal; and

a second source pattern connected to the source sensing terminal, wherein

a surface of each of the semiconductor chips is connected to the first source pattern,

a surface of a reference chip as one of the plurality of semiconductor chips is connected to the second source pattern,

a surface of at least one non-reference chip as one of the semiconductor chips other than the reference chip is not connected to the second source pattern, and

a resistance value of a gate resistance of the reference chip is larger than a resistance value of a gate resistance of the non-reference chip.

2 . The semiconductor device according to claim 1 , wherein

the gate resistance of each of the semiconductor chips is a combination resistance of an external gate resistance externally provided to each of the semiconductor chips and an inner gate resistance located in a chip of each of the semiconductor chips.

3 . The semiconductor device according to claim 2 , wherein

a resistance value of the external gate resistance of the reference chip is larger than a resistance value of the inner gate resistance of the reference chip, and

a resistance value of the external gate resistance of the non-reference chip is equal to or smaller than a half a resistance value of the inner gate resistance of the non-reference chip.

4 . The semiconductor device according to claim 1 , wherein

a resistance value of the external gate resistance of the reference chip is three times or more as large as a resistance value of the external gate resistance of the non-reference chip.

5 . The semiconductor device according to claim 1 , wherein

the gate resistance of each of the semiconductor chips has negative temperature characteristics.

6 . The semiconductor device according to claim 3 , wherein

at least one non-reference chip is two or more and five or less non-reference chips, and

an arrangement pitch of the semiconductor chips is equal to or larger than 5 mm.

7 . The semiconductor device according to claim 1 , wherein

each of the semiconductor chips is made up of a wide bandgap semiconductor.