Semiconductor package having multiple redistribution layers and method of making the same
A semiconductor package comprises two or more chips, a first molding layer, a second molding layer, a third molding layer, a fourth molding layer, a bottom redistribution layer (RDL), a middle RDL, and a top RDL. The two or more chips comprise a first chip and a second chip. The top RDL comprises a first copper plate and a second copper plate. A plurality of vias electrically connect the second copper plate to the second chip. A method comprises the steps of preparing two or more chips; forming a chip-level molding layer; forming a middle RDL; forming a lower-level molding layer; forming a bottom RDL; forming a lowest-level molding layer; forming a top RDL; and forming a top-level molding layer so as to fabricate a semiconductor package.
1 . A semiconductor package comprising:
two or more chips comprising:
a first chip; and
a second chip;
a first molding layer;
a second molding layer, a bottom surface of the second molding layer directly contacting a top surface of the first molding layer;
a third molding layer, a bottom surface of the third molding layer directly contacting a top surface of the second molding layer;
a fourth molding layer, a bottom surface of the fourth molding layer directly contacting a top surface of the third molding layer;
a bottom redistribution layer (RDL) comprising a power input pin, a switching pin and a ground pin, a bottom surface of the bottom RDL exposed from a bottom of the first molding layer, and a top surface of the bottom RDL interfacing a bottom surface of the second molding layer;
a middle RDL, a bottom surface of the middle RDL directly contacting the second molding layer, and a top surface of the middle RDL interfacing a bottom surface of the third molding layer; and
a top RDL, a bottom surface of the top RDL interfacing a top surface of the third molding layer.
2 . The semiconductor package of claim 1 , wherein at least one of the first chip and the second chip comprises a first front surface electrode electrically connected to the ground pin and a back surface electrode electrically connected to the switching pin.
3 . The semiconductor package of claim 1 , wherein the top RDL comprises a copper plate covering substantially an entire back surface of at least one of the first chip and the second chip comprising a back surface electrode electrically connected to a switching pin, wherein the copper plate connects to a plurality of vias connected to the switching pin.
4 . The semiconductor package of claim 3 , wherein the two or more chips further comprises a third chip comprising a plurality of front surface electrodes connected to the middle RDL.
5 . The semiconductor package of claim 1 , wherein the first chip comprises
a first front surface electrode electrically connected to the switching pin, and
a back surface electrode electrically connected to the power input pin; and
wherein the second chip comprises
a first front surface electrode electrically connected to the ground pin, and
a back surface electrode electrically connected to the switching pin.
6 . The semiconductor package of claim 5 ,
wherein the top RDL comprises:
a first copper plate; and
a second copper plate;
wherein the first copper plate covers substantially an entire back surface of the first chip and connects to a first plurality of vias connected to the power input pin; and
wherein the second copper plate covers substantially an entire back surface of the second chip and connects to a second plurality of vias connected to the switching pin.
7 . The semiconductor package of claim 6 ,
wherein a top surface of the first copper plate is covered by the fourth molding layer; and
wherein a top surface of the second copper plate is covered by the fourth molding layer.
8 . The semiconductor package of claim 6 , wherein
the first plurality of vias are arranged along a first direction; and
the second plurality of vias are arranged along a second direction perpendicular to the first direction.
9 . The semiconductor package of claim 5 , wherein the two or more chips further comprise a third chip; wherein a sum of a front surface area of the first chip, a front surface area of the second chip, and a front surface area of the third chip is at least 67% of a top surface area of the semiconductor package.
10 . The semiconductor package of claim 5 , wherein the semiconductor package is a DC-DC buck converter.
11 . The semiconductor package of claim 5 , wherein the semiconductor package is a quad flat no-lead (QFN) package.
12 . A semiconductor package comprising:
two or more chips comprising:
a first chip; and
a second chip;
a first molding layer;
a second molding layer, a bottom surface of the second molding layer directly contacting a top surface of the first molding layer;
a third molding layer, a bottom surface of the third molding layer directly contacting a top surface of the second molding layer;
a fourth molding layer, a bottom surface of the fourth molding layer directly contacting a top surface of the third molding layer;
a bottom redistribution layer (RDL) comprising a power input pin, a switching pin and a ground pin, a bottom surface of the bottom RDL exposed from a bottom of the first molding layer, and a top surface of the bottom RDL interfacing a bottom surface of the second molding layer;
a middle RDL, a bottom surface of the middle RDL directly contacting the second molding layer, and a top surface of the middle RDL interfacing a bottom surface of the third molding layer; and
a top RDL, a bottom surface of the top RDL interfacing a top surface of the third molding layer;
wherein the two or more chips are embedded in the third molding layer;
wherein a respective front surface of each of the two or more chips interfaces the second molding layer; and
wherein a respective back surface of each of the two or more chips interfaces the fourth molding layer.
13 . The semiconductor package of claim 12 , wherein each of the first molding layer, the second molding layer, the third molding layer, and the fourth molding layer comprises a same molding compound with a same filler.
14 . The semiconductor package of claim 12 , wherein each of the first molding layer, the second molding layer, the third molding layer, and the fourth molding layer comprises a different filler material from other molding layers.
15 . The semiconductor package of claim 12 , wherein each of the first molding layer, the second molding layer, the third molding layer, and the fourth molding layer comprises a same molding compound with a same filler; and
wherein each of the first molding layer, the second molding layer, the third molding layer, and the fourth molding layer comprises different percentage amount of filler from other molding layers.
16 . The semiconductor package of claim 12 , wherein bottom RDL further comprises a bottom half-etched portion enclosed inside the first molding layer; and
wherein a total area of the bottom surface of the bottom RDL exposed from the bottom of the first molding layer is less than a total area of the top surface of the bottom RDL interfacing the bottom surface of the second molding layer.
17 . The semiconductor package of claim 12 , wherein a top surface of the top RDL is exposed and coplanar to a top surface of the fourth molding layer.
18 . The semiconductor package of claim 12 , wherein the semiconductor package is a DC-DC buck converter.
19 . The semiconductor package of claim 12 , wherein the semiconductor package is a quad flat no-lead (QFN) package.
20 . A semiconductor package comprising:
two or more metal-oxide-semiconductor field-effect transistor (MOSFET) chips comprising:
a first MOSFET chip comprising:
a source electrode and a gate electrode on a front surface of the first MOSFET chip, and
a drain electrode on a back surface of the first MOSFET chip; and
a second MOSFET chip comprising:
a source electrode and a gate electrode on a front surface of the second MOSFET chip, and
a drain electrode on a back surface of the second MOSFET chip;
a first molding layer;
a second molding layer, a bottom surface of the second molding layer directly contacting a top surface of the first molding layer;
a third molding layer, a bottom surface of the third molding layer directly contacting a top surface of the second molding layer;
a fourth molding layer, a bottom surface of the fourth molding layer directly contacting a top surface of the third molding layer;
a bottom redistribution layer (RDL) comprising a power input pin, a switching pin and a ground pin, a bottom surface of the bottom RDL exposed from a bottom of the first molding layer, and a top surface of the bottom RDL interfacing a bottom surface of the second molding layer;
a middle RDL, a bottom surface of the middle RDL directly contacting the second molding layer, and a top surface of the middle RDL interfacing a bottom surface of the third molding layer; and
a top RDL, a bottom surface of the top RDL interfacing a top surface of the third molding layer; and
wherein the semiconductor package is a DC-DC buck converter.