Current detection circuit and method for improving accuracy of inductor current detection

1 . A current detection circuit for a direct-current to direct-current (DC-DC) converter, the DC-DC converter comprising a high-side transistor and a low-side transistor coupled in series between an input end and a ground with a switch node formed between the high-side transistor and the low-side transistor, the switch node being coupled to an inductor, the current detection circuit comprising:

a first detection circuit configured to detect a current provided by the low-side transistor to the inductor during a turn-on period of the low-side transistor, thereby generating a low-side detecting current; and

a processing circuit comprising a first capacitor having a first end coupled to the ground and configured to perform an operation during a first and a second switch cycle, wherein the operation includes:

outputting a cycle detecting current based on a terminal voltage established at a second end of the first capacitor;

increasing the terminal voltage established on the first capacitor by applying a constant current during a first period of the first switch cycle, wherein the first period is a turn-on period of the high-side transistor or a turn-off period of the low-side transistor;

varying the terminal voltage with the low-side detecting current generated during a second period of the first switch cycle, wherein:

during the first switch cycle, the turn-on period of the high-side transistor comprising a first time point, and a first value of the terminal voltage established on the first capacitor at the first time point; and

during the first switch cycle, the turn-on period of the low-side transistor comprising a second time point, and a second value of the terminal voltage established on the first capacitor at the second time point;

adjusting the magnitude of the constant current during the second switch cycle to be smaller than the magnitude of the constant current during the first switch cycle when the first value is larger than the second value; and

adjusting the magnitude of the constant current during the second switch cycle to be larger than the magnitude of the constant current during the first switch cycle when the first value is smaller than the second value.

2 . The current detection circuit of claim 1 , wherein an interval between the first time point and an end time of the first period in the first switch cycle is smaller than or equal to a first predetermined time length.

3 . The current detection circuit of claim 2 , wherein the first predetermined time length is equal to 10 ns.

4 . The current detection circuit of claim 2 , wherein the first predetermined time length is equal to one-tenth of the first period in the first switch cycle.

5 . The current detection circuit of claim 2 , wherein the first detection circuit includes an operational amplifier, the second time point is after an end time of a setting time of the operational amplifier during the first switch cycle, and a time length between the end time of the setting time and the second time point is smaller than or equal to a second predetermined time length.

6 . The current detection circuit of claim 1 , wherein the processing circuit comprises:

a current-to-voltage converting circuit configured to convert the low-side detecting current outputted by the first detection circuit into a voltage;

a first switch coupled between the second end of the first capacitor and the current-to-voltage converting circuit and configured to be turned off during a first period and turned on during a second period;

a current source circuit configured to provide the constant current;

a second switch coupled between the current source circuit and the second end of the first capacitor and configured to be turned on during the first period and turned off during the second period; and

a voltage-to-current converting circuit coupled to the second end of the first capacitor and configured to convert the terminal voltage established on the first capacitor into the cycle detecting current.

7 . The current detection circuit of claim 6 , wherein the processing circuit further comprises an adjusting circuit coupled to the current source circuit and comprising:

a sample and hold circuit configured to sample the terminal voltages established on the first capacitor, thereby acquiring the first value and the second value;

a comparison circuit configured to compare the first value and the second value provided by the sample and hold circuit, thereby outputting an adjusting signal; and

a current adjusting circuit configured to adjust the magnitude of the constant current provided by the current source circuit during the second switch cycle based on the adjusting signal.

8 . The current detection circuit of claim 7 , wherein the current adjusting circuit comprises:

a trigger configured to output a trigger signal based on the adjusting signal and a clock signal, wherein:

a pulse of the clock signal lasts from a fourth time point to a third time point;

the second time point, the third time point and the fourth time point are in the second period of the first switch cycle;

the third time point is after the second time point; and

the fourth time point is between the second time point and the third time point; and

an up/down counter configured to adjust an output number based on the trigger signal so as to match the magnitude of the constant current provided by the current source circuit with the output number.

9 . The current detection circuit of claim 8 , wherein an interval between the second time point and the fourth time point is larger than or equal to a setup time of the trigger.

10 . The current detection circuit of claim 8 , wherein an interval between the fourth time point and the third time point is larger than or equal to a retaining time of the trigger.

11 . The current detection circuit of claim 7 , wherein the sample and hold circuit comprises:

a voltage buffering circuit coupled to the second end of the first capacitor;

a third switch coupled between the voltage buffering circuit and a first input end of the comparison circuit;

a second capacitor including:

a first end coupled to a first node between the third switch and the first input end of the comparison circuit; and

a second end coupled to the ground;

a fourth switch coupled between the voltage buffering circuit and a second input end of the comparison circuit; and

a third capacitor including:

a first end coupled to a second node between the fourth switch and the second input end of the comparison circuit; and

a second end coupled to the ground.

12 . The current detection circuit of claim 11 , wherein:

the third switch is configured to be switched from a turn-on state to a turn-off state at the first time point and switched from the turn-off state to the turn-on state at the third time point, enabling the second capacitor to retain a voltage of the first value between the first time point and the third time point;

the second time point and the third time point are in the second period of the first switch cycle, and the third time point is after the second time point; and

the fourth switch is configured to be switched from the turn-on state to the turn-off state at the second time point and switched from the turn-off state to the turn-on state at the third time point, enabling the third capacitor to retain a voltage of the second value between the second time point and the third time point.

13 . The current detection circuit of claim 1 , wherein the processing circuit is configured to perform the operation during each switch cycle among multiple sets of switch cycles.

14 . A current detection method for a direct-current to direct-current (DC-DC) converter, the DC-DC converter comprising a high-side transistor and a low-side transistor coupled in series between an input end and a ground, a switch node between the high-side transistor and the low-side transistor being coupled to an inductor, the current detection method, during each switch cycle among a plurality of switch cycles of the DC-DC converter, comprising:

outputting a cycle detecting current based on a terminal voltage established on a second end of a first capacitor, wherein a first end of the first capacitor is coupled to the ground;

detecting a current provided by the low-side transistor to the inductor during a turn-on period of the low-side transistor for acquiring a low-side detecting current;

increasing the terminal voltage established on the first capacitor using a constant current during a first period, wherein the first period is a turn-on period of the high-side transistor or a turn-off period of the low-side transistor;

varying the terminal voltage established on the first capacitor with the low-side detecting current using the low-side detecting current during a second period, wherein:

the first period and the second period forms a switch cycle which includes a first switch cycle and a second switch cycle of the DC-DC converter;

during the first switch cycle, the turn-on period of the high-side transistor comprising a first time point, and a first value of the terminal voltage established on the first capacitor at the first time point; and

during the first switch cycle, the turn-on period of the low-side transistor comprising a second time point, and a second value of the terminal voltage established on the first capacitor at the second time point;

adjusting the magnitude of the constant current during the second switch cycle to be smaller than the magnitude of the constant current during the first switch cycle when the first value is larger than the second value; and

adjusting the magnitude of the constant current during the second switch cycle to be larger than the magnitude of the constant current during the first switch cycle when the first value is smaller than the second value.

15 . The current detection method of claim 14 , wherein an interval between the first time point and an end time of the first period in the first switch cycle is smaller than or equal to a first predetermined time length.

16 . The current detection method of claim 15 , wherein:

the low-side detecting current is detected by a first detection circuit which includes an operational amplifier;

the second time point is after an end time of a setting time of the operational amplifier during the first switch cycle; and

a time length between the end time of the setting time and the second time point is smaller than or equal to a second predetermined time length.