Method for predicting defect in semiconductor device
A method for predicting a defect in a semiconductor device includes: calculating a first probability that particles will be generated in a semiconductor element by radiation; calculating a second probability that damage will occur in the semiconductor element due to the particles; generating a training data set using input data and simulation data, the input data including damage data generated using the first probability and the second probability and including at least one of a position in which the damage will occur and an amount of the damage, impurity concentration of impurities doped in at least a portion of the semiconductor element, and structural data of the semiconductor element, and the simulation data including electrical characteristics of the semiconductor element obtained as a result of a simulation based on the input data; and training a machine learning model based on the training data set to generate a defect prediction model.
1 . A method for predicting a defect in a semiconductor device, the method comprising:
calculating a first probability that particles will be generated in a semiconductor element of the semiconductor device by radiation;
calculating a second probability that damage will occur in the semiconductor element due to the particles;
generating a training data set using input data and simulation data, the input data comprising damage data generated using the first probability and the second probability and comprising at least one of a position in which the damage will occur and an amount of the damage, an impurity concentration of impurities doped in at least a portion of the semiconductor element, and structural data of the semiconductor element, and the simulation data comprising electrical characteristics of the semiconductor element obtained as a result of a simulation based on the input data;
training a machine learning model based on the training data set to generate a defect prediction model;
applying the defect prediction model to a design of the semiconductor device to generate a defect prediction output;
generating an updated design of the semiconductor device based on the defect prediction output of the defect prediction model; and
manufacturing the semiconductor device based on the updated design.
2 . The method of claim 1 , wherein the semiconductor element is a memory cell comprising a transistor and a capacitor.
3 . The method of claim 2 , wherein the capacitor comprises a lower electrode, a dielectric layer, and an upper electrode, and the upper electrode comprises a semiconductor material.
4 . The method of claim 2 , wherein the electrical characteristics of the semiconductor element comprise a resistance value of the memory cell while the transistor is turned on.
5 . The method of claim 1 , wherein the first probability is calculated using a number of the particles generated in the semiconductor element by radiation, as compared with a number of neutrons incident on the semiconductor element.
6 . The method of claim 5 , wherein the number of the neutrons and the number of the particles are predicted using a simulation tool using a radiation transport code.
7 . The method of claim 1 , wherein a plurality of positions are defined in the semiconductor element, and the second probability is predicted for each of the plurality of positions using a simulation tool.
8 . The method of claim 7 , wherein the plurality of positions are defined in a first direction that is perpendicular to an upper surface of a semiconductor substrate of the semiconductor device.
9 . The method of claim 7 , wherein the second probability varies depending on an amount of a semiconductor material included in each of the plurality of positions.
10 . The method of claim 1 , wherein the structural data comprises at least one of a length of a channel of the semiconductor element, a critical dimension of a gate included in the semiconductor element, a critical dimension of a capacitor included in the semiconductor element, and a critical dimension of a buried contact connecting the capacitor to an active region.
11 . The method of claim 1 , wherein the input data is input to a technology computer aided design (TCAD) simulation tool that is configured to calculate resistance of the semiconductor element, and the resistance of the semiconductor element calculated by the TCAD simulation tool is at least a portion of the simulation data used to generate the training data set.