Layout and photomask
View Patent ↗The present disclosure provides a photomask and a method of forming a photomask, in which the photomask may obtain an optimized uniformity via a simplified process flow. The photomask includes a plurality of stair-like patterns parallel disposed with each other, wherein each of the stair-like patterns includes a plurality of first right angles at one side and a plurality of second right angle at another side opposite to the side, and each of the first right angles and each of the second right angles are not in a same vertical axis.
1 . A photomask ( 400 , FIG. 8 ), comprising:
at least one first pattern ( 403 ) comprising a first stair-like edge ( 403 a ) and a second stair-like edge ( 403 b ) opposite to the first stair-like edge, wherein the first stair-like edge comprises a plurality of first right angles (R 3 ), the second stair-like edge comprises a plurality of second right angles (R 4 ), and one of the first right angles and one of the second right angles nearest thereto are not at a same axis (A 2 /A 3 ), wherein each of the first stair-like edge ( 605 a ) and the second stair-like edge ( 605 b ) comprises a plurality of stairs and at least one of the stairs comprises an expanding length (L 4 ) being greater than a length (L 2 ) of other ones of the stairs.
2 . The photomask ( 400 , FIG. 8 ) according to claim 1 , wherein there is a distance (G 3 ) between the one of the first right angles and the one of the second right angles nearest thereto.
3 . The photomask ( 400 , FIG. 8 ) according to claim 1 , wherein each of the stairs comprises a same height (H 1 ).
4 . The photomask ( 700 , FIG. 14 ) according to claim 1 , wherein at least one of the stairs comprises an expanding height (H 3 ) being greater than a height (H 1 ) of other ones of the stairs.
5 . The photomask ( 400 , FIG. 8 ) according to claim 1 , wherein a plurality of the first patterns are in alignment with each other.
6 . The photomask ( 500 , FIG. 10 ) according to claim 5 , further comprising:
a second pattern ( 505 ) comprising a third stair-like edge ( 505 a ) and a fourth stair-like edge ( 505 b ) opposite to the third stair-like edge ( 505 a ), wherein the third stair-like edge comprises a plurality of third right angles (R 3 ), the fourth stair-like edge comprises a plurality of fourth right angles (R 4 ), and one of the third right angles (R 3 ) and one of the fourth right angles (R 4 ) nearest thereto are not at a same axis (A 2 /A 3 ).
7 . The photomask ( 500 , FIG. 10 ) according to claim 6 , wherein the one of the third right angles (R 3 ) on the second patterns ( 505 ) and one of the first angles (R 3 ) on the first pattern ( 503 ) nearest thereto are not at a same axis (A 2 /A 3 ).
8 . A layout disposed on a semiconductor substrate, comprising:
at least one first pattern comprising a first stair-like edge and a second stair-like edge opposite to the first stair-like edge, wherein the first stair-like edge comprises a plurality of first right angles, the second stair-like edge comprises a plurality of second right angles, and one of the first right angles and one of the second right angles nearest thereto are not at a same axis, wherein each of the first stair-like edge ( 605 a ) and the second stair-like edge ( 605 b ) comprises a plurality of stairs and at least one of the stairs comprises an expanding length (L 4 ) being greater than a length (L 2 ) of other ones of the stairs.
9 . The layout disposed on a semiconductor substrate according to claim 8 , wherein there is a distance between the one of the first right angles and the one of the second right angles nearest thereto.
10 . The layout disposed on a semiconductor substrate according to claim 8 , wherein each of the stairs comprises a same height.
11 . The layout disposed on a semiconductor substrate according to claim 8 , wherein at least one of the stairs comprises an expanding height being greater than a height of other ones of the stairs.
12 . The layout disposed on a semiconductor substrate according to claim 8 , wherein a plurality of the first patterns are in alignment with each other.
13 . The layout disposed on a semiconductor substrate according to claim 12 , further comprising:
a second pattern comprising a third stair-like edge and a fourth stair-like edge opposite to the third stair-like edge, wherein the third stair-like edge comprises a plurality of third right angles, the fourth stair-like edge comprises a plurality of fourth right angles, and one of the third right angles and one of the fourth right angles nearest thereto are not at a same axis.
14 . The layout disposed on a semiconductor substrate according to claim 13 , wherein the one of third right angles (R 3 ) on the second patterns ( 505 ) and one of the first angles (R 3 ) on the first pattern ( 503 ) nearest thereto are not at a same axis (A 2 /A 3 ).
15 . A layout disposed on a semiconductor substrate, comprising:
at least one first pattern comprising a first stair-like edge and a second stair-like edge opposite to the first stair-like edge, wherein the first stair-like edge comprises a plurality of first right angles, the second stair-like edge comprises a plurality of second right angles, and one of the first right angles and one of the second right angles nearest thereto are not at a same axis, wherein each of the first stair-like edge ( 705 a ) and the second stair-like edge ( 705 b ) comprises a plurality of stairs and at least one of the stairs comprises an expanding height (H 3 ) being greater than a height (H 1 ) of other ones of the stairs.
16 . The layout disposed on a semiconductor substrate according to claim 15 , wherein each of the stairs comprises a same length.
17 . The layout disposed on a semiconductor substrate according to claim 15 , wherein at least one of the stairs comprises an expanding length being greater than a length of other ones of the stairs.
18 . The layout disposed on a semiconductor substrate according to claim 15 , further comprising a plurality of the first patterns in alignment with each other.
19 . The layout disposed on a semiconductor substrate according to claim 15 , further comprising:
a second pattern comprising a third stair-like edge and a fourth stair-like edge opposite to the third stair-like edge, wherein the third stair-like edge comprises a plurality of third right angles, the fourth stair-like edge comprises a plurality of fourth right angles, and one of the third right angles and one of the fourth right angles nearest thereto are not at a same axis.
20 . The layout disposed on a semiconductor substrate according to claim 15 , wherein there is a distance between the one of the first right angles and the one of the second right angles nearest thereto.