Power supply rejection ratio enhancment techniques for low dropout regulators

1 . A low dropout voltage regulator (LDO) with power supply noise compensation, the LDO comprising:

a first transistor coupled between a voltage supply and an output node, the first transistor having a control terminal;

a first feedback network coupled to the output node and configured to generate an error voltage based on a regulated output voltage of the LDO;

a first amplifier circuit including a first input for receiving a reference voltage and a second input for receiving the error voltage; and

a power supply noise compensation circuit coupled between the voltage supply and the control terminal of the first transistor,

wherein the power supply noise compensation circuit includes:

a second transistor that is a scaled replica of the first transistor, wherein respective voltages at a control terminal, a first terminal, and a second terminal of the second transistor correspond to voltages of the control terminal, a first terminal, and a second terminal of the first transistor, respectively;

a third transistor coupled in series with the second transistor to bias the second transistor with a scaled current through the first transistor;

a second amplifier circuit configured to include a second feedback network that includes the second transistor, the second feedback network generating a power supply noise offset voltage at a third terminal of the second transistor and a corresponding first control terminal voltage at the control terminal of the second transistor; and

a summing circuit to sum an output voltage of the first amplifier circuit with the first control terminal voltage at the control terminal of the second transistor for application to the control terminal of the first transistor for power supply noise compensation of the regulated output voltage.

2 . The LDO of claim 1 , comprising:

a biasing network including a third amplifier circuit and a fourth transistor, wherein the fourth transistor is a scaled replica of the first transistor, wherein respective voltages at a control terminal, a first terminal, and a second terminal of the fourth transistor correspond to voltages of the control terminal, the first terminal, and the second terminal of the first transistor, respectively,

wherein the biasing network is configured to generate the scaled current through the first transistor upon which a bias current of the second transistor is based.

3 . The LDO of claim 1 , wherein the summing circuit comprises:

a pair of transistors, wherein a first one of the pair of transistors is configured to receive the output voltage of the first amplifier circuit and second one of the pair of transistors is configured to receive the first control terminal voltage, wherein the pair of transistors is configured to produce a sum of the output voltage of the first amplifier circuit and the first control terminal voltage.

4 . The LDO of claim 3 , comprising:

a buffer circuit coupled between the summing circuit and the control terminal of the first transistor.

5 . The LDO of claim 1 , comprising:

a current limiting circuit configured to clamp the first control terminal voltage generated by the second amplifier circuit to a specified voltage when the current flowing through the first transistor exceeds a specified current.

6 . The LDO of claim 5 , wherein the current limiting circuit comprises:

a sixth transistor that is a scaled replica of the first transistor, wherein respective voltages at a control terminal, a first terminal, and a second terminal of the sixth transistor correspond to voltages of the control terminal, the first terminal, and the second terminal of the first transistor, respectively; and

a first current source sourcing or sinking the specified current, the first current source coupled to a third terminal of the sixth transistor,

wherein the current limiting circuit is configured such that when the current flowing through the first transistor exceeds the specified current, a seventh transistor is turned on to couple a second current source to a diode-connected eighth transistor to generate the specified voltage.

7 . A method of performing power supply noise compensation in a low dropout voltage regulator (LDO), the method comprising:

receiving a voltage at a control terminal of a first transistor coupled between a voltage supply and an output node and generating a responsive regulated output voltage of the LDO at the output node;

generating an error voltage based on the regulated output voltage of the LDO via a first feedback network coupled to the output node;

biasing a second transistor with a scaled current through the first transistor via a third transistor coupled in series with the second transistor, wherein the second transistor is a scaled replica of the first transistor, and wherein respective voltages at a control terminal, a first terminal, and a second terminal of the second transistor correspond to voltages of the control terminal, a first terminal, and a second terminal of the first transistor, respectively;

generating, via a second amplifier circuit configured to include a second feedback network that includes the second transistor, a power supply noise offset voltage at a third terminal of the second transistor and a corresponding first control terminal voltage at the control terminal of the second transistor; and

controlling the voltage at the control terminal of the first transistor by summing the error voltage and the first control terminal voltage for application to the control terminal of the first transistor for power supply noise compensation of the regulated output voltage.

8 . The method of claim 7 , comprising:

buffering the summed error voltage and the first control terminal voltage.

9 . The method of claim 7 , comprising:

performing current limiting by clamping the first control terminal voltage to a specified voltage when the current flowing through the first transistor exceeds a specified current.

10 . The method of claim 9 , comprising:

coupling a current source to a diode-connected transistor to generate the specified voltage when the current flowing through the first transistor exceeds the specified current.

11 . A method of performing power supply noise compensation in a low dropout voltage regulator (LDO), the method comprising:

receiving a voltage at a control terminal of a first transistor coupled between a voltage supply and an output node and generating a responsive regulated output voltage of the LDO at the output node;

generating an error voltage based on the regulated output voltage of the LDO via a first feedback network coupled to the output node;

controlling the voltage at the control terminal of the first transistor by summing the error voltage and a power supply noise compensation component from a power supply noise compensation circuit; and

when current flowing through the first transistor exceeds a specified current, performing current limiting by coupling a current source to a diode-connected transistor to generate a specified voltage and clamping a first control terminal voltage to the specified voltage.