Adaptive clock gating for improving wear out-induced duty cycle shift in computer clock network
This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
1 . An apparatus for clock gating, the apparatus comprising processing circuitry coupled to memory, the processing circuitry configured to:
detect that gating of a local clock of a computer core is enabled;
detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and
set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
2 . The apparatus of claim 1 , wherein to detect that the clock gating condition is satisfied comprises to detect a clock gate event associated with the local clock, and wherein to set the clock gating polarity of the local clock comprises to switch the clock gating polarity from a first polarity to a second polarity different than the first polarity.
3 . The apparatus of claim 2 , wherein to detect the clock gate event associated with the local clock is unassociated with measuring a duty cycle of the local clock.
4 . The apparatus of claim 2 , wherein the processing circuitry is further configured to:
detect a second clock gate event associated with the local clock; and
switch the clock gating polarity from the second polarity to the first polarity based on the detection of the second clock gate event.
5 . The apparatus of claim 1 , wherein the processing circuitry is further configured to:
start a timer based on the detection that the gating is enabled,
wherein to detect that the clock gating condition is satisfied comprises to determine that the timer has exceeded a maximum polarity holding time period, and
wherein to set the clock gating polarity of the local clock comprises to switch the clock gating polarity from a first polarity to a second polarity different than the first polarity.
6 . The apparatus of claim 5 , wherein the processing circuitry is further configured to:
generate an estimate for the maximum polarity holding time period.
7 . The apparatus of claim 5 , wherein the processing circuitry is further configured to:
reset the timer based on the determination that the timer has exceeded the maximum polarity holding time period.
8 . The apparatus of claim 1 , wherein the processing circuitry is further configured to:
start a timer based on the detection that the gating is enabled;
determine that the timer has not exceeded a maximum polarity holding time period; and
determine that the local clock is not ungated.
9 . The apparatus of claim 1 , wherein the processing circuitry is further configured to:
start a timer based on the detection that the gating is enabled;
determine that the timer has not exceeded a maximum polarity holding time period;
determine that the local clock is ungated; and
store a current polarity of the local clock as a next polarity of the local clock.
10 . The apparatus of claim 1 , wherein the processing circuitry is further configured to:
detect a duty cycle measurement of the local clock,
wherein to detect that the clock gating condition is satisfied comprises to determine that the duty cycle measurement is below a duty cycle threshold, and
wherein to set the clock gating polarity of the local clock comprises to set the clock gating polarity to 1.
11 . The apparatus of claim 1 , wherein the processing circuitry is further configured to:
detect a duty cycle measurement of the local clock,
wherein to detect that the clock gating condition is satisfied comprises to determine that the duty cycle measurement is above a duty cycle threshold, and
wherein to set the clock gating polarity of the local clock comprises to set the clock gating polarity to 0.
12 . The apparatus of claim 1 , wherein the processing circuitry is further configured to:
detect a duty cycle measurement of the local clock;
start a timer based on the detection that the gating is enabled; and
determine, when the timer exceeds a maximum polarity holding time period, that the local clock is gated or ungated.
13 . A non-transitory computer-readable storage medium comprising instructions to cause processing circuitry of a device for clock gating, upon execution of the instructions by the processing circuitry, to:
detect that gating of a local clock of a computer core is enabled;
detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and
set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
14 . The non-transitory computer-readable medium of claim 13 , wherein to detect that the clock gating condition is satisfied comprises to detect a clock gate event associated with the local clock, and wherein to set the clock gating polarity of the local clock comprises to switch the clock gating polarity from a first polarity to a second polarity different than the first polarity.
15 . The non-transitory computer-readable medium of claim 13 , wherein execution of the instructions further causes the processing circuitry to:
start a timer based on the detection that the gating is enabled,
wherein to detect that the clock gating condition is satisfied comprises to determine that the timer has exceeded a maximum polarity holding time period, and
wherein to set the clock gating polarity of the local clock comprises to switch the clock gating polarity from a first polarity to a second polarity different than the first polarity.
16 . The non-transitory computer-readable medium of claim 13 , wherein execution of the instructions further causes the processing circuitry to:
detect a duty cycle measurement of the local clock,
wherein to detect that the clock gating condition is satisfied comprises to determine that the duty cycle measurement is below a duty cycle threshold, and
wherein to set the clock gating polarity of the local clock comprises to set the clock gating polarity to 1.
17 . The non-transitory computer-readable medium of claim 13 , wherein execution of the instructions further causes the processing circuitry to:
detect a duty cycle measurement of the local clock,
wherein to detect that the clock gating condition is satisfied comprises to determine that the duty cycle measurement is above a duty cycle threshold, and
wherein to set the clock gating polarity of the local clock comprises to set the clock gating polarity to 0.
18 . A method for clock gating, the method comprising:
detecting, by processing circuitry of a device, that gating of a local clock of a computer core is enabled;
detecting, by the processing circuitry, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and
setting, by the processing circuitry, a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
19 . The method of claim 18 , wherein detecting that the clock gating condition is satisfied comprises detecting a clock gate event associated with the local clock, and wherein setting the clock gating polarity of the local clock comprises switching the clock gating polarity from a first polarity to a second polarity different than the first polarity.
20 . The method of claim 18 , further comprising:
detecting a duty cycle measurement of the local clock,
wherein detecting that the clock gating condition is satisfied is based on a comparison of the duty cycle measurement to a duty cycle threshold.