Power management interface for multiple software requestors

1 . An apparatus comprising:

a control circuit configured to transition a plurality of power domains into selected ones of a set of performance states;

a set of state request registers, wherein a given state request register includes fields associated with respective ones of the plurality of power domains;

a plurality of processing circuits, including:

a first processing circuit configured to store a first state request value into a first one of the set of state request registers; and

a second processing circuit configured to store a second state request value into a second one of the set of state request registers;

wherein a given state request value indicates a given requested performance state for at least one of the plurality of power domains;

a performance management circuit configured to:

for ones of the plurality of power domains, tally requests in the associated fields in the set of state request registers for ones of the set of performance states;

select, based on results of the tally, a particular performance state of one or more requested performance states for a given one of the plurality of power domains;

determine a performance state transition path to sequence from a current performance state to the selected performance state; and

cause the control circuit to transition to the selected performance state using the performance state transition path.

2 . The apparatus of claim 1 , wherein to store the first state request value into the first state request register, the first processing circuit is further configured to:

store a particular value in a first field of the first state request register, the first field associated with a first power domain of the plurality of power domains, and wherein the particular value indicates a vote for a first performance state of the set of performance states for the first power domain; and

store an abstain value in a second field of the first state request register, the second field associated with a second power domain of the plurality of power domains, and wherein the abstain value indicates no performance state preference for the second power domain.

3 . The apparatus of claim 2 , wherein to select a particular one of the requested performance states for the second power domain, the performance management circuit is further configured to ignore ones of the second field in the set of state request registers that have the abstain value.

4 . The apparatus of claim 1 , wherein the performance management circuit includes a plurality of state machines corresponding to respective ones of the plurality of power domains; and

wherein to cause the control circuit to transition a particular one of the power domains to the selected performance state, the performance management circuit is further configured to use the performance state transition path to sequence a corresponding one of the plurality of state machines through one or more state transitions.

5 . The apparatus of claim 1 , wherein the performance management circuit is further configured to:

in response to a particular power domain entering the particular performance state, set a particular acknowledgement signal that corresponds to a requesting processing circuit that requested the particular performance state for the particular power domain.

6 . The apparatus of claim 5 , wherein a state request register associated with the requesting processing circuit is configured to reject a change from a current value to a different value in the associated field until a corresponding acknowledgement has been received by the requesting processing circuit.

7 . The apparatus of claim 5 , wherein the performance management circuit is further configured to:

determine that a different processing circuit has requested a different performance state for the particular power domain; and

delay causing the control circuit to transition to the different performance state until the particular power domain has entered the particular performance state.

8 . The apparatus of claim 1 , wherein the performance management circuit is further configured to:

determine, using the associated fields in the set of state request registers, a given performance state of the requested performance states for a given one of the plurality of power domains;

compare the given performance state to a floor performance state; and

select the floor performance state in response to a determination that the floor performance state is a higher performance state than the given performance state.

9 . The apparatus of claim 1 , wherein to determine the performance state transition path, the performance management circuit is further configured to determine a transition path that avoids restricted combinations of performance states between the plurality of power domains, wherein the restricted combinations of performance states include incompatible conditions between two or more of the plurality of power domains.

10 . A method comprising:

storing, by a first processing circuit in an integrated circuit (IC), a first requested state value into a first memory location, wherein the first requested state value includes a plurality of fields corresponding to respective ones of a plurality of power domains included in the integrated circuit;

storing, by a second processing circuit in the IC, a second requested state value into a second memory location different from the first memory location, wherein the second requested state value includes the plurality of fields corresponding to the respective ones of the plurality of power domains;

tallying, by a performance management circuit in the IC for ones of the plurality of power domains, requests in the corresponding fields in the first and second requested state values for ones of the plurality of power domains;

determining, by the performance management circuit in the IC, a first performance state for a first power domain of the plurality of power domains, the determining based on results of the tallying for a first field of the first and second requested state values;

determining, by the performance management circuit, a second performance state for a second power domain of the plurality of power domains, the determining based on results of the tallying for a second field of the first and second requested state values; and

causing, by the performance management circuit, the first and second power domains to transition to the respective first and second performance states.

11 . The method of claim 10 , wherein determining the first performance state includes identifying a highest requested state value from the first field of the first and second requested state values; and

wherein determining the second performance state includes identifying a highest requested state value from the second field of the first and second requested state values.

12 . The method of claim 11 , further comprising:

determining, by the performance management circuit, that placing the second power domain into the determined second performance state would result in a restricted condition due to a number of circuit blocks in the IC operating in the second performance state in the second power domain exceeding a threshold number of circuit blocks allowed to concurrently operate at the second performance state; and

in response to determining the restricted condition, placing, by the performance management circuit, the second power domain into a reduced second performance state.

13 . The method of claim 12 , further comprising, in response to a determination that the number of circuit blocks in the IC operating in the second performance state in the second power domain is below the threshold number, placing, by the performance management circuit, the second power domain into an unrestricted second power state.

14 . The method of claim 10 , further comprising:

in response to determining that the first power domain has entered a performance state indicated by the first field of the first requested state value, sending a first acknowledgement signal to the first processing circuit; and

in response to determining that the first power domain has entered a performance state indicated by the first field of the second requested state value, sending a second acknowledgement signal to the second processing circuit.

15 . The method of claim 14 , wherein the storing of the first requested state value by the first processing circuit, includes using firmware to generate and write the first requested state value to the first memory location;

wherein the storing of the second requested state value by the second processing circuit, includes using hardware circuits to generate and write the second requested state value to the second memory location; and

further comprising storing, by the first processing circuit prior to receiving the first acknowledgement signal, a third requested state value into the first memory location, wherein the third requested state value includes a different value for the first field.

16 . A system comprising:

a memory circuit including a plurality of locations;

a control circuit configured to transition one or more power domains of a plurality of power domains into respective ones of a set of performance states;

a processor circuit configured to execute a plurality of processes, wherein the plurality of processes are configured to:

generate respective state values to indicate requested ones of the set of performance states, wherein a given state value includes a plurality of fields associated with respective ones of the plurality of power domains; and

store the respective state values in different locations of the memory circuit; and

a performance management circuit configured to:

read the respective state values from the different locations of the memory circuit;

for ones of the plurality of power domains, tally requests in the associated fields in the different locations of the memory circuit;

for a particular one of the plurality of power domains, select a particular performance state based on results of the tally for the associated fields of the generated state values; and

cause the control circuit to transition to the selected performance state.

17 . The system of claim 16 , wherein to transition the one or more power domains into respective performance states, the performance management circuit is further configured to:

determine respective transition paths for the plurality of power domains from current performance states to selected performance states;

identify, across the respective transition paths, restricted combinations of performance states of the plurality of power domains, wherein the restricted combinations of performance states include an incompatibility between a frequency of a given clock signal and one or more of the plurality of power domains; and

modify the respective transition paths to avoid the restricted combinations.

18 . The system of claim 16 , wherein the performance management circuit is configured to:

in response to a determination that the particular power domain has entered the selected performance state, send a particular acknowledgement to a subset of the plurality of processes that requested the selected performance state.

19 . The system of claim 18 , wherein a given one of the subset of processes is configured to:

prior to receiving the particular acknowledgement, generate a new state value indicating a change to a different performance state for the particular power domain;

receive the particular acknowledgement from the performance management circuit; and

receive, after receiving the particular acknowledgement, a different acknowledgement indicating that the particular power domain has entered the different performance state.

20 . The system of claim 16 , wherein the performance management circuit is further configured to:

determine, using the associated fields in a given state value generated by a given process, that a requested performance state for a given power domain of the plurality of power domains is less than floor performance state assigned to the given power domain; and

select the floor performance state in response to the determination.