Asymmetrical power sharing

Inventors: Doron Rajwan (Rishon LeZion, IL); Jamie L. Langlinais (Los Gatos, CA); Kevin I. Park (Oakland, CA)

Assignee: Apple Inc.

G06F1/263 G06F1/3206

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Quick Facts

Patent No.: US 12681547
App. No.: 18/392,770
Granted: Jul 14, 2026
Kind: B2

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Abstract

Techniques are disclosed relating to managing power allocation for component circuits coupled to one or more power sources. A system can include a first integrated circuit die that is indirectly coupled to a second integrated circuit die through a set of intervening integrated circuit dies. The system can include a first power source configured to supply power to component circuits of the first and second integrated circuit dies. The first integrated circuit may allocate, to a first set of component circuits of the first integrated circuit die, a first set of power credits for obtaining power from the first power source. The first integrated circuit may send a second set of power credits to the second integrated circuit die through the set of intervening integrated circuit dies without the set of intervening integrated circuit dies using the second set of power credits to obtain power from the first power source.

Claims (34)

1 . A system, comprising:

a plurality of integrated circuit dies, wherein a first one of the plurality of integrated circuit dies is indirectly coupled to a second one of the plurality of integrated circuit dies through a path that includes a plurality of intervening integrated circuit dies, wherein the first and second integrated circuit dies implement a type of computing resource that is not implemented on the plurality of intervening integrated circuit dies; and

a first power source that is configured to supply power to component circuits of the first and second integrated circuit dies but is not coupled to supply power to the plurality of intervening integrated circuit dies,

wherein the first and second integrated circuit dies are configured to obtain power from the first power source based on first power credits allocated for the first power source that are actively shared between the first and second integrated circuit dies, and wherein the first integrated circuit die is configured to send a set of the first power credits to the second integrated circuit die through the path without any of the set of power credits being used by the plurality of intervening integrated circuit dies to obtain power from the first power source,

wherein the plurality of intervening integrated circuit dies is configured to obtain power from a second power source based on second power credits allocated for the second power source that are distinct from the first power credits allocated for the first power source.

2 . The system of claim 1 , wherein the plurality of intervening integrated circuit dies is configured to share the second power credits with each other without sending the second power credits through other integrated circuit dies.

3 . The system of claim 1 , wherein the second power source is configured to supply power to component circuits of the first and second integrated circuit dies, wherein the first and second integrated circuit dies are configured to obtain power from the second power source based on the second power credits, and wherein the first integrated circuit die is configured to send a set of the second power credits to the second integrated circuit die through the path.

4 . The system of claim 3 , wherein the first and second power sources are different types of power sources.

5 . The system of claim 3 , wherein the first integrated circuit die is coupled to a multiplexor circuit that is configured to send, on a same set of lanes of a die-to-die interface, power credits of a first given power source before power credits of a second given power source.

6 . The system of claim 3 , wherein the second power source is a battery.

7 . The system of claim 1 , wherein the second power source is not coupled to supply power to the first and second integrated circuit dies.

8 . The system of claim 1 , wherein the first and second integrated circuit dies include a first type of processor but not a second type of processor, and the plurality of intervening integrated circuit dies include the second type of processor but not the first type of processor.

9 . The system of claim 1 , wherein the type of computing resource is a first type of processor, and the plurality of intervening integrated circuit dies includes a second type of processor that is not implemented on the first and second integrated circuit dies.

10 . A method, comprising:

accessing, by a first integrated circuit die, information identifying a power budget of a first power source that is configured to supply power to the first integrated circuit die and a second integrated circuit die but is not coupled to supply power to a plurality of intervening integrated circuit dies that couple the first integrated circuit die to the second integrated circuit die, wherein power is obtainable from the first power source based on a first plurality of power credits included in the power budget;

allocating, by the first integrated circuit die, a first set of the first plurality of power credits to a set of component circuits of the first integrated circuit die; and

sending, by the first integrated circuit die, a second set of the first plurality of power credits to the second integrated circuit die through a path that includes the plurality of intervening integrated circuit dies without the plurality of intervening integrated circuit dies using the second set of power credits to obtain power from the first power source, wherein the first and second integrated circuit dies implement a type of computing resource that is not implemented on the plurality of intervening integrated circuit dies, and wherein the plurality of intervening integrated circuit dies is configured to obtain power from a second power source based on a second plurality of power credits allocated for the second power source that is distinct from the first plurality of power credits allocated for the first power source.

11 . The method of claim 10 , further comprising:

sending, by the first integrated circuit die, a third set of power credits to a particular one of the plurality of intervening integrated circuit dies, wherein the particular intervening integrated circuit die is configured to obtain, based on the third set of power credits, power from the second power source, wherein the second power source is configured to supply power to the first and second integrated circuit dies.

12 . The method of claim 11 , wherein the second set of credits is sent before the third set of credits on a same set of lanes of a die-to-die interface that connects the first integrated circuit die to the particular intervening integrated circuit die.

13 . The method of claim 10 , further comprising:

receiving, by the first integrated circuit die and from the second integrated circuit die, a third set of power credits for the first power source; and

allocating, by the first integrated circuit die, power to the set of component circuits of the first integrated circuit die based on the third set of power credits.

14 . The method of claim 10 , wherein the second power source is not coupled to supply power to the first and second integrated circuit dies.

15 . The method of claim 10 , wherein the first and second integrated circuit dies include central processing unit (CPU) processors but not graphics processing unit (GPU) processors while the plurality of intervening integrated circuit dies include GPU processors but not CPU processors.

16 . A non-transitory computer-readable medium having stored thereon design information specifying a circuit design in a format recognizable by a fabrication system that is configured to use the design information to fabricate a hardware integrated assembly that comprises:

wherein the first integrated circuit die is configured to:

allocate, to a first set of component circuits of the first integrated circuit die, a first set of a first plurality of power credits allocated for the first power source, wherein the first set of component circuits is configured to obtain power from the first power source based on the first set of power credits; and

send, to the second integrated circuit die through the path, a second set of the first plurality of power credits, wherein the second integrated circuit die is configured to obtain power from the first power source based on the second set of power credits,

wherein the plurality of intervening integrated circuit dies is configured to obtain power from a second power source based on a second plurality of power credits allocated for the second power source that is distinct from the first plurality of power credits allocated for the first power source.

17 . The medium of claim 16 , wherein the first and second integrated circuit dies are not configured to utilize the second plurality of power credits to obtain power from the second power source.

18 . The medium of claim 16 , wherein the plurality of intervening integrated circuit dies is configured to obtain power from the second power source based on actively shared power credits of the second plurality of power credits without sending those power credits through other integrated circuit dies.