Storage device, system-on-chip including the storage device, and computing apparatus

1 . A storage device comprising:

a storage module comprising a plurality of latch units each being assigned with an address, an input end of each of the plurality of latch units being configured to receive write data; and

a clock gating module comprising a first stage of clock gating units and a second stage of clock gating units coupled between the plurality of latch units and the first stage of clock gating units,

wherein each clock gating unit of the first stage of clock gating units is configured to receive an input clock signal and an enable signal obtained based on first address decoding of a write address and output an enable clock signal to a respective clock gating unit of the second stage of clock gating units, and each clock gating unit of the second stage of clock gating units is configured to receive an enable clock signal outputted by a respective clock gating unit of the first stage of clock gating units and an enable signal obtained based on second address decoding of the write address and output an enable clock signal to a respective latch unit of the plurality of latch units.

2 . The storage device according to claim 1 , wherein the clock gating module further comprises one or more stages of clock gating units coupled between the first stage of clock gating units and the second stage of clock gating units, and each clock gating unit of each stage of clock gating units of the one or more stages of clock gating units is configured to receive an enable clock signal outputted by a respective clock gating unit of an upper stage of clock gating units of the one or more stages of clock gating units and an enable signal obtained based on respective address decoding of the write address and output an enable clock signal to a respective clock gating unit of a lower stage of clock gating units of the one or more stages of clock gating units,

wherein each clock gating unit of the first stage of clock gating units is configured to receive the input clock signal and the enable signal obtained based on the first address decoding of the write address and output the enable clock signal to a respective clock gating unit of an uppermost stage of clock gating units of the one or more stages of clock gating units, and each clock gating unit of the second stage of clock gating units is configured to receive an enable clock signal outputted by a respective clock gating unit of a lowermost stage of clock gating units of the one or more stages of clock gating units and the enable signal obtained based on the second address decoding of the write address and output the enable clock signal to the respective latch unit of the plurality of latch units.

3 . The storage device according to claim 2 , wherein the plurality of latch units are grouped at levels, and groups obtained from grouping the plurality of latch units at each level is obtained by further dividing groups obtained from grouping the plurality of latch units at an upper level,

wherein a number of stages of clock gating units comprised in the clock gating module corresponds to a number of levels for grouping the plurality of latch units, and

wherein a number of clock gating units comprised in each stage of clock gating units in the clock gating module corresponds to a number of groups obtained from grouping the plurality of latch units at a respective level.

4 . The storage device according to claim 1 , wherein the plurality of latch units are grouped at levels, and groups obtained from grouping the plurality of latch units at each level is obtained by further dividing groups obtained from grouping the plurality of latch units at an upper level,

wherein a number of stages of clock gating units comprised in the clock gating module corresponds to a number of levels for grouping the plurality of latch units, and

wherein a number of clock gating units comprised in each stage of clock gating units in the clock gating module corresponds to a number of groups obtained from grouping the plurality of latch units at a respective level.

5 . The storage device according to claim 4 , wherein the enable signal received by each clock gating unit of each stage of clock gating units in the clock gating module is obtained based on address decoding of the write address corresponding to the respective level.

6 . The storage device according to claim 5 , wherein an address of each latch unit of the plurality of latch units comprises different parts corresponding to different levels, and wherein addresses of latch units in a same group at a same level have a same part.

7 . The storage device according to claim 6 , wherein the address is binary, and wherein address decoding of the write address corresponding to each level is associated with respective several bits of the write address.

8 . The storage device according to claim 5 , wherein the address is binary, and wherein address decoding of the write address corresponding to each level is associated with respective several bits of the write address.

9 . The storage device according to claim 8 , wherein a number of bits of the respective several bits is decided by a number of bits of a binary representation of a ratio of a number of groups obtained from grouping the plurality of latch units at the level to a number of groups obtained from grouping the plurality of latch units at an upper level.

10 . The storage device according to claim 4 , wherein each clock gating unit of the first stage of clock gating units is coupled, via other stage of clock gating units in the clock gating module, to a respective group of latch units obtained from grouping the plurality of latch units at a first level, and each clock gating unit of the second stage of clock gating units is coupled to a respective group of latch units obtained from grouping the plurality of latch units at a second level below the first level.

11 . The storage device according to claim 1 , wherein

the storage module further comprises an additional latch unit assigned with an address, an input end of the additional latch unit being configured to receive the write data;

the clock gating module further comprises an additional clock gating unit coupled to the additional latch unit and configured to receive the input clock signal and an enable signal obtained based on address decoding of the write address and output an enable clock signal to the additional latch unit.

12 . The storage device according to claim 1 , further comprising:

a flip-flop unit configured to output the write data to the storage module based on a received clock signal;

a clock source unit coupled to the flip-flop unit and the clock gating module, respectively, and configured to provide the input clock signal; and

a clock delay unit coupled between the clock source unit and the flip-flop unit, and configured to receive the input clock signal and delay the input clock signal based on a delay of the enable clock signal received by a latch unit corresponding to the write address in the storage module relative to the input clock signal, and output the delayed input clock signal to the flip-flop unit.

13 . The storage device according to claim 12 , wherein the clock delay unit comprises one or more of: a clock buffer; an inverter.

14 . The storage device according to claim 12 , wherein:

the flip-flop unit is triggered by a rising edge, a rising edge of the delayed input clock signal is closer to a rising edge of the enable clock signal received by the latch unit corresponding to the write address in the storage module compared with a rising edge of the input clock signal; or

the flip-flop unit is triggered by a falling edge, a falling edge of the delayed input clock signal is closer to a falling edge of the enable clock signal received by the latch unit corresponding to the write address in the storage module compared with a falling edge of the input clock signal.

15 . A system-on-chip comprising the storage device according to claim 1 .

16 . A computing apparatus comprising the system-on-chip according to claim 15 .