Alternate physical layer power mode
A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.
1 . An apparatus comprising:
physical layer (PHY) circuitry configured to alternatively support a plurality of different power control settings, wherein the plurality of different power control settings comprises a first power control setting for normal operation and a second power control setting for short-reach channel applications;
a PHY Interface for the PCI Express (PIPE)-based interface to couple the PHY circuitry to a media access control (MAC) layer, wherein the PIPE-based interface comprises a plurality of pins, a power control signal is to be received from the MAC layer at the PHY circuitry on a subset of the plurality of pins, and the power control signal identifies a selection of one of the plurality of different power control settings to apply during operation;
wherein the PHY circuitry is to apply parameters of the selected one of the plurality of different power control settings based on the power control signal, the first power control setting comprises use of alternating current (AC)-coupling by the PHY circuitry on the interconnect, and the second power control setting comprises use of direct current (DC)-coupling by the PHY circuitry on the interconnect.
2 . The apparatus of claim 1 , wherein the PIPE-based interface further comprises a data interface, a command interface, and a status interface.
3 . The apparatus of claim 2 , wherein the data interface is implemented by a set of data pins in the plurality of pins, the command interface is implemented by a set of command pins in the plurality of pins, and the status interface is implemented by a set of status pins in the plurality of pins.
4 . The apparatus of claim 1 , wherein the PHY circuitry comprises a physical coding sublayer.
5 . The apparatus of claim 1 , wherein the parameters comprise a channel loss parameter.
6 . The apparatus of claim 1 , wherein the parameters of the first power control setting comprise a first receiver equalization parameter and the parameters of the second power control setting comprises a different second receiver equalization parameter.
7 . The apparatus of claim 1 , wherein the parameters of the first power control setting comprise use of a receiver detect state defined in a state machine, and the parameters of the second power control setting comprise bypass of the receiver detect state.
8 . The apparatus of claim 1 , wherein the power control signal comprises a code, wherein the code comprises a two-bit code, a first value of the code is to indicate that the first power control setting is to be applied by the PHY circuitry, and a second value of the code is to indicate that the second power control setting is to be applied by the PHY circuitry.
9 . The apparatus of claim 1 , wherein the subset of the plurality of pins comprises two or more pins.
10 . The apparatus of claim 1 , wherein the parameters comprise, for each of the plurality of power control settings, a respective receiver equalization parameter and a respective channel loss parameter.
11 . The apparatus of claim 1 , wherein the second power control setting corresponds to implementation of the physical layer associated with a die-to-die link in a multi-chip package.
12 . The apparatus of claim 1 , further comprising a PHY integrated circuit (IC) device comprising the PHY circuitry and the interface, wherein the PHY IC device is discrete from the MAC layer.
13 . The apparatus of claim 1 , further comprising a microcell comprising the PHY circuitry and the interface.
14 . An apparatus comprising:
a media access control (MAC) layer block;
a PHY Interface for the PCI Express (PIPE)-based interface to couple to a physical layer device, wherein the PIPE-based interface comprises a plurality of power control pins to carry a code to indicate to the physical layer device a particular one of at least two power control settings to be implemented on the physical layer device,
wherein the MAC layer block comprises circuitry to generate the code at the power control pins to indicate the particular power control setting to the physical layer device and the particular power control setting comprises settings for a short-reach link, wherein the at least two power control settings have different respective parameters to apply at the physical layer device, and the parameters of the particular power control setting comprise use of direct current (DC)-coupling at the PHY circuitry instead of alternating current (AC)-coupling.
15 . The apparatus of claim 14 , wherein the MAC layer block comprises circuitry to generate signals according to a particular interconnect protocol.
16 . The apparatus of claim 15 , wherein the MAC layer block further comprises state machine logic to implement a link training and status state machine of the particular interconnect protocol, and a receiver detect state of the link training and status state machine is to be bypassed in accordance with the particular power control setting.
17 . The apparatus of claim 15 , wherein the particular interconnect protocol comprises one of a protocol based on PCIe, USB, SATA, Display Port, or Converged IO.
18 . A system comprising:
a first die on a package; and
a second die on the package, wherein the first die is coupled to the second die on the package by an interconnect, and the second die comprises a port to couple to the interconnect, and the port comprises:
media access control (MAC) circuitry; and
physical layer (PHY) circuitry discrete from the MAC circuitry, wherein the PHY circuitry is configured to alternatively support a plurality of different operational power control settings, wherein the plurality of different operational power control settings comprises a first power control setting for normal operation and a second power control setting for short-reach channel applications,
wherein the MAC circuitry couples with the PHY circuitry through a PHY Interface for the PCI Express (PIPE)-based interface comprising a data interface, a command interface, and a status interface, wherein the PIPE-based interface comprises a plurality of power control pins to carry a signal from the MAC circuitry to the PHY circuitry to indicate a particular one of the plurality of operational power control settings to be implemented by the PHY circuitry during communication of data over the data interface,
wherein the first power control setting comprises use of alternating current (AC)-coupling by the PHY circuitry on the interconnect, and the second power control setting comprises use of direct current (DC)-coupling by the PHY circuitry on the interconnect.
19 . The system of claim 18 , wherein the parameters of the first power control setting comprise use of a receiver detect state defined in a state machine, and the parameters of the second power control setting comprise bypass of the receiver detect state.
20 . The system of claim 19 , wherein the receiver detect state is to be bypassed to proceed directly to a polling state in the state machine based on the parameters of the second power control setting.
21 . The system of claim 18 , wherein the PHY circuitry is to implement a physical layer of the link according to a particular interconnect protocol, wherein at least some of the particular operational power control settings are to be applied to the physical layer of the link.
22 . The apparatus of claim 1 , wherein the power control signal is defined as a unidirectional signal oriented from the MAC layer to the PHY circuitry.