Access time in a memory array

Inventors: Rajiv Kumar Sisodia (Bangalore, IN); Andy Wangkun Chen (Austin, TX); Yew Keong Chong (Austin, TX); Prashantkumar Jayantilal Vaghasia (Austin, TX); Vishal Thakre (Austin, TX); Jaspreet Singh (Bangalore, IN); Sreelekha Nallagatla (Bangalore, IN)

Assignee: Arm Limited

G06F3/0613 G06F3/0659 G06F3/0673

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Quick Facts

Patent No.: US 12,681,643
App. No.: 18/651,526
Granted: Jul 14, 2026
Kind: B2

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Abstract

A memory device includes a bitcell array having at least a first plurality of first adjacent bitcell banks and a second plurality of second adjacent bitcell banks. One or more bitcell array input lines are coupled to the bitcell array at a first physical location between the first adjacent bitcell banks. One or more bitcell array output lines are coupled to the bitcell array at a second physical location between the second adjacent bitcell banks. The one or more bitcell array input lines are further coupled from the first plurality of adjacent bitcell banks to the second plurality of bitcell banks at a physical location between the second plurality of adjacent bitcell banks. The one or more bitcell array output lines are further coupled from the second plurality of bitcell banks to the first plurality of bitcell banks at a physical location between the first plurality of bitcell banks.

Claims (31)

1 . A memory device, comprising:

a bitcell array comprising at least a plurality of first adjacent bitcell banks and a plurality of second adjacent bitcell banks;

one or more bitcell array input lines coupled to the bitcell array at a first physical location between the first adjacent bitcell banks; and

one or more bitcell array output lines coupled to the bitcell array at a second physical location between the plurality of second adjacent bitcell banks;

wherein the one or more bitcell array input lines are further coupled from the plurality of first adjacent bitcell banks to the plurality of second adjacent bitcell banks at a physical location between the plurality of second adjacent bitcell banks, and the one or more bitcell array output lines are further coupled from the plurality of second adjacent bitcell banks to the plurality of first adjacent bitcell banks at a physical location between the plurality of first adjacent bitcell banks.

2 . The memory device of claim 1 , wherein a physical location between each respective plurality of bitcell banks comprises a physical location nearer a geometric center of each respective plurality of bitcell banks than edges of each respective plurality of bitcell banks.

3 . The memory device of claim 1 , wherein the one or more bitcell array input lines are configured to provide one or more of clock, address, input data, and control signals, and are configured to provide a clock input signal to a local clock circuit for each plurality of adjacent bitcell banks in the bitcell array.

4 . The memory device of claim 1 , wherein the one or more bitcell array output lines are configured to provide data read from bitcells as a memory read operation output.

5 . The memory device of claim 4 , wherein the one or more bitcell array output lines of respective pluralities of adjacent bitcell banks other than the plurality of second adjacent bitcell banks comprises an inverter, an amplifier, or a combination thereof, and are inverted with respect to the bitcell array output lines of the plurality of second adjacent bitcell banks.

6 . The memory device of claim 1 , wherein the bitcell array further comprises a third plurality of adjacent bitcell banks physically located between the first adjacent bitcell banks and the plurality of second adjacent bitcell banks.

7 . The memory device of claim 6 , the third plurality of adjacent bitcell banks further coupled to the one or more bitcell array input lines and the one or more bitcell array output lines at a third physical location between the third plurality of adjacent bitcell banks.

8 . A non-transitory computer-readable medium storing computer-readable code for fabrication of the memory device of claim 7 .

9 . A non-transitory computer-readable medium storing computer-readable code for fabrication of the memory device of claim 1 .

10 . A memory device, comprising:

a bitcell array comprising at least a first group of one or more first adjacent bitcell banks and a second group of one or more second adjacent bitcell banks;

one or more bitcell array input electrical connections coupled to the bitcell array at a first physical location more proximate to the first group of one or more first adjacent bitcell banks than to the second group of one or more second adjacent bitcell banks; and

one or more bitcell array output electrical connections coupled to the bitcell array at a second physical location more proximate to the second group of one or more second adjacent bitcell banks than to the first group of one or more first adjacent bitcell banks;

wherein the one or more bitcell array input electrical connections are further coupled from the first group of one or more first adjacent bitcell banks to the second group of one or more second adjacent bitcell banks at a physical location more proximate to the second group of one or more second adjacent bitcell banks than to the first group of one or more first adjacent bitcell banks, and the one or more bitcell array output electrical connections are further coupled from the second group of one or more second adjacent bitcell banks to the first group of one or more first adjacent bitcell banks at a physical location more proximate to the first group of one or more first adjacent bitcell banks than to the second group of one or more second adjacent bitcell banks.

11 . The memory device of claim 10 , wherein a physical location more proximate to each respective group of bitcell banks comprises a physical location nearer a geometric center of each respective group of bitcell banks than a geometric center of one or more groups of bitcell banks other than the respective group of bitcell banks.

12 . The memory device of claim 10 , wherein the one or more bitcell array input electrical connections are configured to provide one or more of clock, address, input data, and control signals, and are configured to provide a clock input signal to a local clock circuit for each group of adjacent bitcell banks in the bitcell array.

13 . The memory device of claim 10 , wherein the one or more bitcell array output electrical connections are configured to provide data read from bitcells as a memory read operation output.

14 . The memory device of claim 13 , wherein the one or more bitcell array output electrical connections of respective pluralities of adjacent bitcell banks other than the one or more second adjacent bitcell banks comprises an inverter, an amplifier, or a combination thereof, and are inverted with respect to the one or more bitcell array output electrical connections of the one or more second adjacent bitcell banks.

15 . The memory device of claim 10 , wherein the bitcell array further comprises a third group of adjacent bitcell banks physically located in proximity to the first group of adjacent bitcell banks and to the second group of adjacent bitcell banks.

16 . The memory device of claim 15 , the third group of adjacent bitcell banks further coupled to the one or more bitcell array input electrical connections and the one or more bitcell array output electrical connections at a third physical location more proximate to the third group of one or more third adjacent bitcell banks than to the first group of one or more first adjacent bitcell banks or the second group of one or more second adjacent bitcell banks.

17 . A method of operating a memory bitcell array, comprising:

receiving an input signal in a first group of one or more first adjacent bitcell banks comprising a part of the memory bitcell array, the input signal received via one or more bitcell array input electrical connections coupled to the memory bitcell array at a first physical location more proximate to the first group of one or more first adjacent bitcell banks than to a second group of one or more second adjacent bitcell banks;

providing an output signal from a second group of one or more second adjacent bitcell banks comprising part of the memory bitcell array, the output signal provided via one or more bitcell array output electrical connections coupled to the memory bitcell array at a second physical location more proximate to the second group of one or more second adjacent bitcell banks than to the first group of one or more first adjacent bitcell banks;

18 . The method of operating a memory bitcell array of claim 17 , wherein the memory bitcell array further comprises one or more third adjacent bitcell banks located in proximity to the one or more first adjacent bitcell banks and the one or more second adjacent bitcell banks, the one or more third adjacent bitcell banks further coupled to the one or more bitcell array input electrical connections and the one or more bitcell array output electrical connections at a third physical location more proximate to the one or more third adjacent bitcell banks than to the first group of one or more first adjacent bitcell banks or the second group of one or more second adjacent bitcell banks.

19 . The method of operating a memory bitcell array of claim 17 , wherein the one or more bitcell array output electrical connections of respective pluralities of adjacent bitcell banks other than the one or more second adjacent bitcell banks comprises an inverter, an amplifier, or a combination thereof, and are inverted with respect to the one or more bitcell array output electrical connections of the one or more second adjacent bitcell banks.

20 . The method of operating a memory bitcell array of claim 17 , wherein the one or more bitcell array input electrical connections are configured to provide one or more of clock, address, input data, and control signals, and the one or more bitcell array output electrical connections are configured to provide data read from bitcells as a memory read operation output.