Efficient command protocol
This document describes apparatuses and techniques for an efficient command protocol for memory access. In various aspects, a memory controller may implement combined operations of different command types (e.g., an activation command plus a read, an activation command plus a write, or an activation command plus a pre-charge command) to better utilize a multiple clock ratio of a command bus (e.g., a (1.5+0.5)N operation in a dual clocking WCK2CK ratio of 4:1), which may improve utilization of a data bus for associated memory responses. By so doing, the efficient command protocol may improve power efficiency and system level performance of a computing system.
1 . A method comprising:
combining an activation command of a host with another memory command of the host to provide a combined memory command, the other memory command comprising a read command, a write command, a pre-charge command, or a refresh command;
communicating, via a command bus of the host and during two periods of a clock at which the command bus operates, the combined memory command to a memory device, wherein communication of the activation command via the command bus as an uncombined activation command consumes over one period of the clock at which the command bus operates; and
receiving, responsive to the combined memory command and via a data bus, a response from the memory device comprising a series of contiguous bits on the data bus.
2 . The method of claim 1 , further comprising:
receiving the activation command; or
determining that the activation command is queued.
3 . The method of claim 2 , further comprising:
in response to receiving the activation command or determining that the activation command is queued, selecting the read command, the write command, the pre-charge command, or the refresh command to combine with the activation command.
4 . The method of claim 1 , wherein the other command is a second memory command, the method further comprises communicating, via the command bus, a third memory command, and wherein:
the second memory command is the read command and the third memory command is another read command;
the second memory command is the write command and the third memory command is another write command;
the second memory command is the pre-charge command and the third memory command is a read command; or
the second memory command is the refresh command and the third memory command is a read command.
5 . The method of claim 1 , further comprising:
communicating, with the combined memory command, a flag or indication to the memory device useful to implement the combined memory command.
6 . The method of claim 5 , wherein the flag or indication comprises one of:
an Auto Pre-charge flag (AP);
an All Bank flag (AB); or
a Burst Order flag (BO).
7 . The method of claim 1 , wherein:
the activation command or the other memory command are formatted as a 16 bit-length command (BL16 command); or
the command bus is configured to operate in compliance with a Low-Power Double Data Rate 5 (LPDDR5) specification or a Low-Power Double Data Rate 6 (LPDDR6) specification.
8 . The method of claim 1 , wherein the other memory command comprises a second read command, and the method further comprises:
communicating, via the command bus and before communicating the combined memory command, a first read command to the memory device;
communicating, via the command bus and after communicating the combined memory command, a third read command to the memory device, and wherein:
the series of contiguous bits received on the data bus comprise respective data bits read from the memory device responsive to the first read command, the second read command, and the third read command.
9 . An apparatus comprising:
a queue to receive commands from a host;
an interface for a memory interconnect comprising a command bus and a data bus; and
a command processor configured to:
combine an activation command of the host with another memory command of the host to provide a combined memory command configured to consume, during communication via the command bus, at least two periods of a clock at which the command bus of the memory interconnect operates, the other memory command comprising a read command, a write command, a pre-charge command, or a refresh command;
communicate, via the command bus and during two periods of the clock at which the command bus of the memory interconnect operates, the combined memory command to a memory device coupled to the memory interconnect, wherein communication of the activation command as an uncombined command consumes over one period of the clock at which the command bus operates; and
receive, responsive to the combined memory command and via the data bus, a response from the memory device comprising a series of contiguous bits on the data bus.
10 . The apparatus of claim 9 , wherein:
prior to the communication of the combined memory command, the command processor communicates a first read command;
the other memory command comprises a second read command;
after the communication of the combined memory command, the command processor communicates a third read command; and
the series of contiguous bits received on the data bus comprise respective data bits read from the memory device responsive to the first read command, the second read command, and the third read command.
11 . The apparatus of claim 9 , wherein the command processor is further configured to:
communicate, with the combined memory command, a flag or indication to the memory device useful to implement the combined memory command.
12 . The apparatus of claim 11 , wherein the flag or indication comprises one of:
an Auto Pre-charge flag (AP);
an All Bank flag (AB); or
a Burst Order flag (BO).
13 . The apparatus of claim 9 , wherein the command processor is further configured to:
receive the activation command; or
determine that the activation command is queued.
14 . The apparatus of claim 9 , wherein the command processor is further configured to:
in response to the reception of the activation command or the determination that the activation command is queued, select the read command, the write command, the pre-charge command, or the refresh command to combine with the activation command.
15 . A system comprising:
a memory device comprising an array of memory cells;
a memory interconnect coupled to the memory device, the memory interconnect comprising a command bus and a data bus; and
a memory controller coupled to the memory interconnect, the memory controller configured to:
combine an activation command of a host with another memory command of the host to provide a combined memory command configured to consume, during communication via the command bus, a multiple of a period of a clock at which the command bus operates, the other memory command comprising a read command, a write command, a pre-charge command, or a refresh command;
communicate, via the command bus, the combined memory command to the memory device coupled to the memory interconnect, wherein communication of the activation command via the command bus as an uncombined command consumes over one period of the clock at which the command bus operates; and
receive, responsive to the combined memory command and via the data bus, a response from the memory device comprising a series of contiguous bits on the data bus.
16 . The system of claim 15 , wherein the memory controller is further configured to:
communicate, with the combined memory command, a flag or indication to the memory device useful to implement the combined memory command.
17 . The system of claim 16 , wherein the flag or indication comprises one of:
an Auto Pre-charge flag (AP);
an All Bank flag (AB); or
a Burst Order flag (BO).
18 . The system of claim 15 , wherein the memory controller is further configured to:
receive the activation command; or
determine that the activation command is queued.
19 . The system of claim 18 , wherein the memory controller is further configured to:
in response to the reception of the activation command or the determination that the activation command is queued, select the read command, the write command, the pre-charge command, or the refresh command to combine with the activation command.
20 . The system of claim 15 , wherein the other command is a second memory command, and the memory controller is further configured to:
communicate, via the command bus, a third memory command, and wherein:
the second memory command is the read command and the third memory command is another read command;
the second memory command is the write command and the third memory command is another write command;
the second memory command is the pre-charge command and the third memory command is a read command; or
the second memory command is the refresh command and the third memory command is a read command.