Nonvolatile memory access via memory interconnect systems
A memory card, for use with a host system, combines both: (i) non-volatile memory express (NVMe) data storage such as a solid state drive (SSD) with (ii) dynamic random access memory (DRAM) conforming to the computer express link (CXL) protocol. The SSD and CXL DRAM share a common controller. CXL memory requests from the host system are handled according to the CXL.io protocol. NVMe data requests are wrapped into a CXL request packet. The common front end identifies the NVMe data request(s) within the CXL packet, parses the NVMe data request, and routes the request to the NVMe memory. A host operating system software driver intercepts the NVMe memory requests and wraps them into the CXL request packet.
1 . An apparatus comprising:
a first memory comprising a dynamic random access memory (DRAM), wherein the DRAM is volatile and configured for data reads and writes according to a first memory access protocol;
a second memory comprising a non-volatile (NV) memory configured for data reads and writes according to a second memory access protocol, wherein the first memory access protocol and the second memory access protocol are different hardware interface protocols; and
a shared device controller configured to:
receive memory requests comprising DRAM write request packets formatted according to the first memory access protocol;
parse a given memory request according to the first memory access protocol and, upon detecting a memory write request indicator, identify a non-volatile memory express (NVME) write command embedded in a memory request packet associated with the given memory request;
determine if the given memory request received from a host system is a write request
(i) destined for the first memory when the given memory request comprises a DRAM write request packet without the memory write request indicator or
(ii) destined for the second memory because the given memory request comprises a DRAM write request packet comprising the memory write request indicator indicating a data transfer to the second memory;
write to the DRAM using the first memory access protocol when the given memory request received from the host system is determined to be the write request destined for the first memory; and
when the given memory request is determined to be the write request destined for the second memory, extract a physical region page (PRP) list from the identified NVME write command and perform the write to the NV memory using the second memory access protocol and the extracted PRP list, without requiring host resubmission or conversion by the host system.
2 . The apparatus of claim 1 , wherein the shared device controller comprises:
a command router configured to receive the given memory request and to parse the given memory request to determine a memory destination from among the first memory and the second memory.
3 . The apparatus of claim 2 , further comprising a front end configured to interface with both of a bus of the host system and the command router, wherein the command router receives the given memory request from the host system via the front end.
4 . The apparatus of claim 1 , wherein the first memory and the second memory together form a single unit dual type memory, wherein the single unit dual type memory comprises physical region pages that correspond to physical region pages of a system volatile memory separate from the single unit dual type memory.
5 . The apparatus according to claim 1 , wherein the DRAM is configured to be expanded and host memory mapped.
6 . The apparatus according to claim 1 , wherein the shared device controller is configured to cause data associated with a write command destined for the second memory to be stored in physical region pages in one of the first memory and a system DRAM, before the data is written to the second memory in accordance with the write command.
7 . The apparatus according to claim 6 , wherein the shared device controller is configured to cause the data associated with the write command destined for the second memory to be stored in the physical region pages of the first memory, before the data is written to the second memory in accordance with the write command.
8 . The apparatus according to claim 1 , wherein the shared device controller is configured to determine and assemble the PRP list.
9 . A tangible, non-transitory, computer readable storage medium comprising instructions which, when executed by a processor of a host system, causes the processor to execute a method comprising:
accessing a first memory comprising a dynamic random access memory (DRAM) being volatile and accessed via a first memory access protocol, and accessing a second memory comprising a non-volatile (NV) memory, via a second memory access protocol, wherein the first memory access protocol and the second memory access protocol are different hardware interface protocols;
parsing a given memory access command according to the first memory access protocol and, upon detecting a memory write request indicator, identifying a non-volatile memory express (NVME) write command embedded in a memory request packet associated with the given memory access command;
determining if the given memory access command generated by the host system is a write request (i) destined for the first memory when the given memory access command comprises a DRAM memory write request packet without the memory write request indicator or (ii) destined for the second memory to be performed via the NV memory coupled with the host system, because the given memory access command comprises a DRAM write request packet with the memory write request indicator indicating a data transfer to the second memory;
wherein when the given memory access command is determined to be a write request destined for the second memory, extracting a physical region page (PRP) list from the identified NVME write command and performing the write to the NV memory using the second memory access protocol and the extracted PRP list, without requiring host resubmission or conversion by the host system; and when the given memory access command is determined to be a write request destined for the first memory, data is written to the first memory.
10 . The tangible, non-transitory, computer readable storage medium of claim 9 , further comprising storing the command packet in a submission queue (SQ) associated with the host system.